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參數(shù)資料
| 型號： | AD805 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Data Retiming Phase-Locked Loop(重定時PLL) |
| 中文描述： | 數(shù)據(jù)定時鎖相環(huán)（重定時鎖相環(huán)） |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 388K |
| 代理商： | AD805 |
AD805
–9–
REV. 0
Table I. Evaluation Board,
Negative Supply: Components List
Reference
Designator
Description
Quantity
R1–8
R9–12
R13, 14, 17, 18, 23, 24 Resistor, 80.6
, 1%
R15, 16, 19–22
C2
C3–12, C15
Z1
Z2
Resistor, 100
, 1%
Resistor, 154
, 1%
8
4
6
6
1
11
1
Resistor, 130
, 1%
10
μ
F, Tantalum
0.1
μ
F, Ceramic Chip
AD805
10H116, ECL Line Receiver 1
Vectron CO-434Y VCXO
AT&T 157-Type VCXO
1
1
Z3
100
1
0.1
1
1000
100
10
0.1
10
JITTER FREQUENCY – kHz
J
CCITT TYPE A MASK
VECTRON
AT&T
Figure 15. AD805-VCXO Circuit Jitter Tolerance
0
–10
–20
1
10
1000
100
–15
–5
JITTER FREQUENCY – kHz
J
VECTRON 1.3 UI
INPUT JITTER
AT&T 1.3 UI
INPUT JITTER
CCITT TYPE B
MASK
Figure 16. AD805-VCXO Circuit Jitter Transfer
155.52 MBPS CLOCK RECOVERY AND DATA RETIMING
USING A SURFACE ACOUSTIC WAVE (SAW) FILTER
The AD805 can be used with a 155.52 MHz SAW filter circuit
for clock recovery and data retiming. In this type of application
(refer to Figure 17), the SAW filter circuit is used to generate a
155.52 MHz clock from the input data. The AD805 data retiming
loop formed by the voltage-controlled phase shifter, the phase
detector and the loop filter, act to servo the phase of the input
data to the phase of the recovered clock. The AD805 can
compensate up to
±
180
°
phase variance through the SAW filter
circuit. The AD805 replaces the D Flip-Flop and phase shifter
components found in traditional SAW filter-based clock recovery
and data retiming circuits. Use of the AD805 eliminates the
phase shifter to SAW filter matching needed to get traditional
SAW filter-based circuits to perform over operating conditions.
The jitter bandwidth and the output jitter of the overall circuit is
determined largely by the SAW filter used. The AD805 retimes
the input data to the recovered clock and buffers the recovered
clock from the SAW filter circuit. The AD805 plays a role in the
jitter accommodation of the overall circuit. The AD805’s phase
shifter range and the bandwidth of the data retiming loop
provide for at least 2 UI p-p jitter tolerance to 1 MHz. The
length of a transitionless block of data that will not cause the
circuit to lose lock or start making bit errors is determined by
the Q of the SAW filter used.
Figure 17 shows a schematic of the AD805 used with a
Toyocom TQS-610J-6R SAW filter. The circuit that precedes
the SAW filter feeds the filter with a pulse at each data transi-
tion. The line receiver circuit that immediately follows the SAW
filter provides gain to the SAW filter output to drive the AD805
CLKIN signals.
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