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參數(shù)資料
| 型號： | AD8026AR-REEL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 運動控制電子 |
| 英文描述： | Quad High Speed Amplifier |
| 中文描述： | QUAD OP-AMP, 6000 uV OFFSET-MAX, PDSO14 |
| 封裝： | PLASTIC, SOIC-14 |
| 文件頁數(shù)： | 6/8頁 |
| 文件大小： | 217K |
| 代理商： | AD8026AR-REEL |
AD8026
–6–
REV. 0
FREQUENCY – Hz
100
10k
100M
100k
1M
10M
0.1
0.01
10
1
O
V
1G
Figure 15. Output Impedance vs. Frequency
FREQUENCY – Hz
1M
10k
100M
100k
1M
10M
1k
100
10k
I
V
1G
100k
10
Figure 16. Input Impedance vs. Frequency
FREQUENCY – Hz
20
–10
–20
10
0
N
1
100k
0
V
24.9
V
49.9
V
100
V
R
S
3k
V
1875
V
+
–
C
L
5k
V
V
IN
= 50mV rms
C
L
= 100pF
1M
10M
100M
500M
Figure 17. Bandwidth and Flatness vs. Series Resistance
into 100 pF
THEORY OF OPERATION
The AD8026, a quad voltage feedback amplifier with rail-to-rail
output swing, is internally configured for a gain of either –5/3 or
+8/3. The gain-setting resistors are laser trimmed for precise
control of their ratio. In addition, the amplifier’s frequency
response has been adjusted to compensate for the parasitic
capacitances associated with the gain resistors and with the
amplifier’s inverting input. The result is an amplifier with very
tight control of closed-loop gain and settling time.
The amplifier’s input stage will operate with voltages from about
–0.2 V below the negative supply voltage to within about 1V of
the positive supply. Exceeding these values will not cause phase
reversal at the output; however, the input ESD protection de-
vices will begin to conduct if the input voltages exceed the sup-
ply rails by greater than 0.5 V. The gain resistors that connect to
Pins 2, 6, 9, and 13 are protected from ESD in such a way that
the voltages applied to these pins may exceed the negative sup-
ply by as much as –7 V.
The rail-to-rail output range of the AD8026 is provided by a
complementary common-emitter output stage. The chosen
circuit topology allows the outputs to source and sink 50 mA of
output current and, with the use of an external series resistor, to
achieve rapid settling time while driving capacitive loads within
0.5 V of the supply rails.
Output Referred Offset Voltage
The output referred offset voltage for a voltage feedback ampli-
fier can be estimated with the following equation:
(
V
OOS
=
V
IOS
×
1
+
R
F
/
R
G
where:
V
OOS
= output referred offset voltage,
V
IOS
= input referred offset voltage,
I
OS
= difference of the two input currents,
I
B
= average of the two input currents,
R
P
= total resistance in series with positive input,
R
F
= 5 k
, R
G
= 3 k
for this part.
This equation leads to the well known conclusion that, for a
voltage feedback amplifier to maintain minimum output offset
voltage, the value of R
P
should be selected to match the parallel
combination of R
F
and R
G
. It should be noted that the AD8026
was designed for an assumed source impedance, of 500
driv-
ing the +Input. Therefore, the value of R
P
included on the chip
is 500
less than the ideal value for minimum output offset.
Additional resistance may be added externally, in series with the
+Input, if the part is to be driven by a lower impedance source.
)
+
I
OS
×
R
F
i
R
G
(
)
+
I
B
×
R
P
R
F
i
R
G
(
)
(
)
APPLICATIONS
The AD8026 is designed with on-chip resistors for each op amp
to provide accurate fixed gain and low output-referenced offset
voltages. This can result in significant cost and board-space savings
for systems that can take advantage of the AD8026 specifications.
The part is actually trimmed in three steps. First, the supply
current of the part is trimmed. Then the gain is accurately
trimmed to specification. This trim adjusts the values of either
the gain or feedback resistor for a ratio of 5 to 3. The final trim
is for the offset voltage. For this trim, the –Input is connected to
ground and the +Input is connected to ground via 500
, while
internal offset resistors are trimmed.
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