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參數(shù)資料
| 型號： | AD8013 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 運動控制電子 |
| 英文描述： | Single Supply Low Power,Triple Video Amplifier(單電源,低功耗,三通道視頻放大器) |
| 中文描述： | 單電源低功耗，三路視頻放大器（單電源，低功耗，三通道視頻放大器） |
| 文件頁數(shù)： | 11/12頁 |
| 文件大?。?/td> | 256K |
| 代理商： | AD8013 |
–11–
REV. A
AD8013
FREQUENCY – Hz
1.5
1.0
–2.0
1M
1G
10M
G
100M
0.5
0
–0.5
–1.0
–1.5
G = +2
R
L
= 150
V
S
= +5V
V
S
=
±
5V
Figure 34. Closed-Loop Gain Matching vs. Frequency
FREQUENCY – Hz
10
8
2
4
6
–1.0
0.5
0
–0.5
1.0
100k
100M
1M
G
10M
V
S
= +5V
V
S
=
±
5V
G = +2
R
L
= 150
G = +2
R
L
= 150
DELAY
MATCHING
DELAY
V
S
= +5V
V
S
=
±
5V
Figure 35. Group Delay and Group Delay Matching
vs. Frequency, G = +2, R
L
= 150
Disable Mode Operation
Pulling the voltage on any one of the Disable pins about 1.6V
up from the negative supply will put the corresponding
amplifier into a disabled, powered down, state. In this
condition, the amplifier’s quiescent current drops to about
0.3 mA, its output becomes a high impedance, and there is
a high level of isolation from input to output. In the case of
the gain of two line driver for example, the impedance at the
output node will be about the same as for a 1.6 k
resistor
(the feedback plus gain resistors) in parallel with a 12 pF
capacitor and the input to output isolation will be about
66 dB at 5 MHz.
Leaving the Disable pin disconnected (floating) will leave
the corresponding amplifier operational, in the enabled
state. T he input impedance of the disable pin is about 40 k
in parallel with a few picofarads. When driven to 0 V, with
the negative supply at –5 V, about 100
μ
A flows into the
disable pin.
When the disable pins are driven by complementary output
CMOS logic, on a single 5 V supply, the disable and enable
times are about 50 ns. When operated on dual supplies,
level shifting will be required from standard logic outputs to
the Disable pins. Figure 36 shows one possible method
which results in a negligible increase in switching time.
+5V
10k
TO DISABLE PIN
V
I
V
I
HIGH => AMPLIFIER ENABLED
V
I
LOW => AMPLIFIER DISABLED
–5V
4k
8k
Figure 36. Level Shifting to Drive Disable Pins on Dual
Supplies
T he AD8013’s input stages include protection from the large
differential input voltages that may be applied when disabled.
Internal clamps limit this voltage to about
±
3 V. T he high input to
output isolation will be maintained for voltages below this limit.
3:1 Video Multiplexer
Wiring the amplifier outputs together will form a 3:1 mux with
excellent switching behavior. Figure 37 shows a recommended
configuration which results in –0.1 dB bandwidth of 35 MHz
and OFF channel isolation of 60 dB at 10 MHz on
±
5 V
supplies. T he time to switch between channels is about 50 ns.
Switching time is virtually unaffected by signal level.
665
75
V
IN
1
84
845
DISABLE 1
V
OUT
75
75
CABLE
–V
S
7
6
5
4
+V
S
1
665
75
V
IN
2
84
845
DISABLE 2
14
13
12
2
665
75
V
IN
3
84
845
8
9
10
3
11
DISABLE 3
Figure 37. A Fast Switching 3:1 Video Mux (Supply
Bypassing Not Shown)
10
0%
100
90
200ns
500mV
5V
Figure 38. Channel Switching Characteristic for the
3:1 Mux
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