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| 型號(hào)： | AD8004AR-14-REEL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | Quad 3000 V/us, 35 mW Current Feedback Amplifier |
| 中文描述： | QUAD OP-AMP, 5000 uV OFFSET-MAX, PDSO14 |
| 封裝： | PLASTIC, SOIC-14 |
| 文件頁(yè)數(shù)： | 12/16頁(yè) |
| 文件大?。?/td> | 271K |
| 代理商： | AD8004AR-14-REEL7 |
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REV. B
AD8004
–12–
Table I. Recommended Component Values and Typical Bandwidths
Alternate
–2
Alternate
–1
Alternate
+1
Alternate
+2
Gain
AD8004AN (DIP)
PACKAGE TYPE
R
F
(
)
R
G
(
)
R
T
(
)
Small Signal BW
@
±
5 V
S
(MHz)
Peaking @
±
5 V
S
0.1 dB Flatness
@
±
5 V
S
(MHz)
Small Signal BW
@ +5 V
S
(MHz)
AD8004AR (SOIC)
PACKAGE TYPE
R
F
(
)
R
G
(
)
R
T
(
)
Small Signal BW
@
±
5 V
S
(MHz)
Peaking @
±
5 V
S
0.1 dB Flatness
@
±
5 V
S
(MHz)
Small Signal BW
@ +5 V
S
(MHz)
–10
–2
–1
+1
+2
+10
499
49.9
None
698
348
57.6
499
249
61.9
649
649
53.6
499
499
54.9
1.21 k
–
50
806
–
50
1.10 k
1.10 k
50
698
698
50
499
54.9
50
155
< 0.3 dB
125
None
180
0.3 dB
135
None
190
0.3 dB
150
1.3 dB
250
1.7 dB
115
< 0.14 dB
185
0.4 dB
135
< 0.3 dB
–
25
–
30
–
–
–
35
–
–
135
105
155
120
160
130
200
95
150
120
499
49.9
None
698
348
57.6
499
249
61.9
750
750
53.6
499
499
54.9
1.10 k
–
50
698
–
50
1.10 k
1.10 k
50
604
604
50
499
54.9
50
155
< 0.7 dB
130
< 0.1 dB
190
0.5 dB
125
None
195
0.4 dB
150
1.3 dB
225
1.8 dB
110
< 0.1 dB
175
0.5 dB
135
< 0.2 dB
–
35
–
25
–
–
–
30
–
–
135
115
175
110
165
130
195
95
155
120
NOTES
1
R
chosen for 50
characteristic input impedance.
2
Resistor values listed are standard 1% tolerance.
The PCB should have a ground plane covering all unused por-
tions of the component side of the board to provide a low im-
pedance ground path. The ground plane should be removed
from the area near the input pins to reduce stray capacitance.
Chip capacitors should be used for supply bypassing (see
Figure 38). One end should be connected to the ground plane
and the other within 1/8 in. of each power pin. An additional
(4.7
μ
F–10
μ
F) tantalum electrolytic capacitor should be con-
nected in parallel.
The feedback resistor should be located close to the inverting
input pin in order to keep the stray capacitance at this node to a
minimum. Capacitance greater than 1 pF at the inverting input
will significantly affect high speed performance when operating
at low noninverting gains. An example of extra inverting input
capacitance can be seen on Figure 35 plot.
Stripline design techniques should be used for long signal traces
(greater than about 1 in.). These should be designed with the
proper system characteristic impedance and be properly termi-
nated at each end.
NONINVERTING CONFIGURATION
C1
0.1
m
F
C2
0.1
m
F
C4
10
m
F
C3
10
m
F
R
T
V
IN
V
OUT
+V
S
–V
S
R
G
R
F
R
bT
, 50
V
1/4
C1
0.1
m
F
C2
0.1
m
F
C4
10
m
F
C3
10
m
F
R
T
V
IN
V
OUT
+V
S
–V
S
R
G
R
F
R
bT
, 50
V
1/4
INVERTING CONFIGURATION
Figure 38. Inverting and Noninverting Configurations
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