參數(shù)資料
型號(hào)： AD7865
廠商： Analog Devices, Inc.
英文描述： Simultaneous Sampling, Fast, 14-Bit ADC(四通道,同時(shí)采樣,高速,14位A/D轉(zhuǎn)換器)
中文描述： 同步采樣，快速，14位ADC（四通道，同時(shí)采樣，高速，14位的A / D轉(zhuǎn)換器）
文件頁(yè)數(shù)： 6/21頁(yè)
文件大?。?/td> 375K
代理商： AD7865
AD7865
–6–
Rev. PrC
PRELMNARY
The selection is latched on the rising edge of
CONVST
. See Selecting a conversion
sequence.
TECHNCAL
input determines whether Channel 1 is included in the channel conversion sequence.
PIN FUNCTION DESCRIPTION
Pin
Mnemonic
Description
1
BUSY
Busy Output. The busy output is triggered high by the rising edge of
CONVST
and
remains high until conversion is completed on all selected channels.
2
FRSTDATA
First Data Output. FRSTDATA is a logic output which, when high, indicates that
the Output Data Register Pointer is addressing Register 1 - See Accessing the Output
Data Registers
3
CONVST
Convert Start Input. Logic Input. A low to high transition on this input puts all
track/hold's into their hold mode and starts conversion on the selected channels. In
addition, the state of the Channel Sequence Selection is also latched on the rising
edge of
CONVST
.
4
CS
active.
5
RD
Read Input. Active low logic input which is used in conjunction with
CS
low to
enable the data outputs. Ensure the
WR
pin is at logic high while performing a read
operation.
6
WR
Write Input. A rising edge on the
WR
input, with
CS
low and
RD
high, latches the
logic state on DB0 to DB3 into the channel select register.
7
CLK IN/SL1
Conversion Clock Input/Hardware Channel Select. The function of this pin depends
upon the
H
/S SEL input. When the
H
/S SEL input is high (choosing software
control of the channel selection sequence), this pin assumes its CLK IN function.
CLK IN is an externally applied clock which allows the user to control the conver-
sion rate of the AD7865. Each conversion needs fifteen clock cycles in order for the
conversion to be completed. The clock should have a duty cycle which is no worse
than 60/40. See Using an External Clock.
When the
H
/S SEL input is low (choosing hardware control of the channel conver-
sion sequence), this pin assumes its Hardware Channel Select function. The SL1
8
INT
/EXT CLK/SL2
Internal/External Clock/Hardware Channel Select. The function of this pin depends
upon the
H
/S SEL input. When the
H
/S SEL input is high (choosing software
control of the channel selection sequence), this pin assumes its
INT
/EXT CLK
function. When
INT
/EXT CLK is at a logic 0, the AD7865 uses its internally
generated master clock. When
INT
/EXT CLK is at logic 1, the master clock is
generated externally to the device and applied to CLK IN.
When the
H
/S SEL input is low (choosing hardware control of the channel conver-
sion sequence), this pin assumes its Hardware Channel Select function. The SL2
input determines whether Channel 2 is included in the channel conversion sequence.
The selection is latched on the rising edge of
CONVST
. See Selecting a conversion
sequence.
9 -10
SL3 - SL4
Hardware Channel Select. The SL3 input determines whether Channel 3 is included
in the channel conversion sequence while SL4 determines whether Channel 4 is
included in the channel conversion sequence.When the pin is at logic 1 the channel is
included in the conversion sequence. When the pin is at logic 0 the channel is
excluded from the conversion sequence. The selection is latched on the rising edge
of
CONVST
. See Selecting a conversion sequence.
11
H
/S SEL
Hardware/Software Select Input. When this pin is at a logic 0, the AD7865 conver-
sion sequence selection is controlled via the SL1 - SL4 input pins and runs off an
internal clock. When this pin is at logic 1, the sequence is controlled via the channel
select register. See Selecting a conversion sequence.
相關(guān)PDF資料
PDF描述
AD7868 Complete 12-bit I/O System Containing a DAC And an ADC(完備的12位I\O系統(tǒng)（包含一個(gè)A/D轉(zhuǎn)換器和一個(gè)D/A轉(zhuǎn)換器）)
AD7869 Complete 14-bit I/O System Containing a DAC and a ADC(完備的14位I/O系統(tǒng)（包含一個(gè)A/D轉(zhuǎn)換器和一個(gè)D/A轉(zhuǎn)換器）)
AD7870AJN LC2MOS Complete, 12-Bit, 100 kHz , Sampling ADC
AD7874AN LC2MOS 4-Channel, 12-Bit Simultaneous Sampling Data Acquisition System
AD7874AQ LC2MOS 4-Channel, 12-Bit Simultaneous Sampling Data Acquisition System
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD7865AS-1 制造商:Rochester Electronics LLC 功能描述:4 CH. SIMULTANEOUS BIPOLAR,14-B ADC I.C. - Bulk 制造商:Analog Devices 功能描述:Analog-Digital Converter IC Number of Bi
AD7865AS-1REEL 制造商:Analog Devices 功能描述:ADC Single SAR 350ksps 14-bit Parallel 44-Pin MQFP T/R 制造商:Rochester Electronics LLC 功能描述:4 CH. SIMULTANEOUS BIPOLAR,14-B ADC I.C. - Tape and Reel
AD7865AS2 制造商:AD 功能描述:*
AD7865AS-2 制造商:Analog Devices 功能描述:ADC Single SAR 350ksps 14-bit Parallel 44-Pin MQFP 制造商:Analog Devices 功能描述:IC 14-BIT ADC
AD7865AS-2REEL 制造商:Analog Devices 功能描述:ADC Single SAR 350ksps 14-bit Parallel 44-Pin MQFP T/R 制造商:Analog Devices 功能描述:ADC SGL SAR 350KSPS 14BIT PARALLEL 44MQFP - Tape and Reel
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