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| 型號(hào)： | AD7865 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Simultaneous Sampling, Fast, 14-Bit ADC(四通道,同時(shí)采樣,高速,14位A/D轉(zhuǎn)換器) |
| 中文描述： | 同步采樣，快速，14位ADC（四通道，同時(shí)采樣，高速，14位的A / D轉(zhuǎn)換器） |
| 文件頁(yè)數(shù)： | 4/21頁(yè) |
| 文件大小： | 375K |
| 代理商： | AD7865 |
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AD7865
TIMING CHARACTERISTICS
1,2
–4–
Rev. PrC
PRELMNARY
DATA
0
ns min
0
ns min
5
ns min
5
ns min
TECHNCAL
ns min
A, B
Versions
Parameter
Units
Test Conditions/Comments
t
CONV
2.5
15
3
0.35
No. of Channels
x (t
CONV
+ t
9
) - t
9
2
6
35
70
μs max
clock cycles
μs max
μs max
Conversion Time, Internal Clock
Conversion Time, External Clock
CLKIN = 5MHz
Acquisition Time
Selected number of channels multiplied by
(t
CONV
+
EOC
pulse width) -
EOC
pulse width
STBY
rising edge to
CONVST
rising edge
STBY
rising edge to
CONVST
rising edge
CONVST
Pulse Width
CONVST
t
ACQ
t
BUSY
μs max
μs max
ms max
ns min
ns min
t
WAKE-UP
- External Vref
t
WAKE-UP
- InternalVref
5
t
1
t
2
Read Operation
t
3
t
4
t
5
t
6
0
0
35
ns min
ns min
ns min
Data Access Time After Falling Edge of
RD
, V
DRIVE
= 5V
ns max
Data Access Time After Falling Edge of
RD,
V
DRIVE
= 3V
Bus Relinquish Time After Rising Edge of
RD
ns max
ns min
Time between consecutive reads
ns min
ns max
ns max
RD
rising edge to FRSTDATA edge (rising or falling)
ns max
EOC
falling edge to FRSTDATA falling delay
ns min
EOC
to
RD
delay
CS
to
RD
Setup Time
CS
to
RD
Hold Time
Read Pulse Width
3
35
40
t
7
4
5
ns min
30
10
75
180
70
15
0
t
8
t
9
t
10
t
11
t
12
Write Operation
t
13
t
14
t
15
t
16
t
17
20
WR
Pulse Width
WR
to
CS
Hold Time
Input data Set up Time ot Rising edge of
WR
Input data Hold Time
NOTES
1
Sample tested at 25°C to ensure compliance. All input signals are measured with tr = tf = 1ns (10% to 90% of +5V) and timed from a voltage level of +1.6 V.
2
See Figures 7, 8 and 9.
3
Measured with the load circuit of Figure 2 and defined as the time required for an output to cross 0.8 V or 2.0 V.
4
These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back to remove the effects of charging
or discharging the 50pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances.
5
Refer to the section, "Standby Mode Operation". The MAX specification of 6ms is valid when using a 0.1μF decoupling capacitor on the V
REF
pin.
Specifications subject to change without notice.
(V
D=
= +5 V ±5%, AGND=DGND= 0V, V
REF
= Internal, Clock = Internal,
All Specifications T
MIN
to T
MAX
unless otherwise noted).
Figure 2. Load Circuit for Access Time and Bus Relinquish Time
TO
OUTPUT
PIN
+1.6V
1.6mA
400μA
50pF
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| AD7865AS-2REEL | 制造商:Analog Devices 功能描述:ADC Single SAR 350ksps 14-bit Parallel 44-Pin MQFP T/R 制造商:Analog Devices 功能描述:ADC SGL SAR 350KSPS 14BIT PARALLEL 44MQFP - Tape and Reel |
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