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參數(shù)資料
| 型號： | AD7865 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Simultaneous Sampling, Fast, 14-Bit ADC(四通道,同時采樣,高速,14位A/D轉(zhuǎn)換器) |
| 中文描述： | 同步采樣，快速，14位ADC（四通道，同時采樣，高速，14位的A / D轉(zhuǎn)換器） |
| 文件頁數(shù)： | 18/21頁 |
| 文件大?。?/td> | 375K |
| 代理商： | AD7865 |
AD7865
–18–
Rev. PrC
DATA
TECHNCAL
conversion results are read using the following 68000
instruction:
CS
RD
WR
BUSY
CONVST
DB0-DB13
AD7865
V
IN1
V
IN2
V
IN3
V
IN4
PA0
INTn
RD
WE
D0-D13
DS
A0-A13
TMS320C5x
ADDRESS
DECODE
AD7864MC68000 Interface
An interface between the AD7864 and the MC68000 is
shown in Figure 22. The conversion can be initiated from
the MC68000 or from an external source. The AD7865
BUSY line can be used to interrupt the processor or,
alternatively, software delays can ensure that conversion
has been completed before a read to the AD7865 is
attempted. Because of the nature of its interrupts, the
68000 requires additional logic (not shown in Figure 22)
mation on 68000 interrupts, consult the 68000 users
manual.
The MC68000
AS
and R/
W
outputs are used to generate a
separate
RD
input signal for the AD7865.
CS
is used to
drive the 68000
DTACK
input to allow the processor to
MOVE.W ADC,D0
where D0 is the 68000 D0 register and ADC is the
AD7865 address.
MICROPROCESSOR INTERFACING
The high speed parallel interface of the AD7865 allows
easy interfacing to most DSPs and microprocessors. The
AD7865 interface of the AD7865 consists of the data lines
(DB0 to DB13),
CS
,
RD
,
WR
,
EOC
and BUSY.
AD7865ADSP-2100/2101/2102 Interface
Figure 20 shows an interface between the AD7865 and the
ADSP-2100. The
CONVST
signal can be generated by
the ADSP-2100 or from some other external source
.
Figure 20 shows the
CS
being generated by a combination
of the
DMS
signal and the address bus of the ADSP2100.
In this way the AD7865 is mapped into the data memory
spcae of the ADSP2100.
The AD7865 BUSY line provides an interrupt to the
ADSP-2100 when the conversion sequence is complete on
all the selected channels. The conversion results can then
be read from the AD7865 using successive read opera-
tions. Alternately, one can use the
EOC
pulse to interrupt
the ADSP-2100 when the conversion on each channel is
complete when reading between each conversion in the
conversion sequence (figure. 8). The AD7865 is read
using the following instruction
MR0 = DM(ADC)
where MR0 is the ADSP-2100 MR0 register and ADC is
the AD7865 address.
CS
RD
WR
BUSY
CONVST
DB0-DB13
AD7865
V
IN1
V
IN2
V
IN3
V
IN4
DT1/F0
IRQn
RD
WR
D0-D13
DMS
A0-A13
ADSP-2100/1/2
ADDRESS
DECODE
Figure 20. AD7865–ADSP-2100 Interface
.
AD7865TMS320C5x Interface
Figure 21 shows an interface between the AD7865 and the
TMS320C5x. As with the previous interfaces, conversion
can be initiated from the TMS320C5x or from an
external source and the processor is interrupted when the
conversion sequence is completed. The
CS
signal to the
AD7865 drived from the DS signal and a decode of the
address bus. This maps the AD7865 into external data
memory. The RD signal from the TMS320 is used to
enable the ADC data onto the data bus. The AD7865 has
a fast parallel bus so there are no wait state requirements.
The following instruction is used to read the conversion
results from the AD7865:
IN D,ADC
where D is Data Memory address and ADC is the
AD7865 address.
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|---|---|
| AD7865AS-1 | 制造商:Rochester Electronics LLC 功能描述:4 CH. SIMULTANEOUS BIPOLAR,14-B ADC I.C. - Bulk 制造商:Analog Devices 功能描述:Analog-Digital Converter IC Number of Bi |
| AD7865AS-1REEL | 制造商:Analog Devices 功能描述:ADC Single SAR 350ksps 14-bit Parallel 44-Pin MQFP T/R 制造商:Rochester Electronics LLC 功能描述:4 CH. SIMULTANEOUS BIPOLAR,14-B ADC I.C. - Tape and Reel |
| AD7865AS2 | 制造商:AD 功能描述:* |
| AD7865AS-2 | 制造商:Analog Devices 功能描述:ADC Single SAR 350ksps 14-bit Parallel 44-Pin MQFP 制造商:Analog Devices 功能描述:IC 14-BIT ADC |
| AD7865AS-2REEL | 制造商:Analog Devices 功能描述:ADC Single SAR 350ksps 14-bit Parallel 44-Pin MQFP T/R 制造商:Analog Devices 功能描述:ADC SGL SAR 350KSPS 14BIT PARALLEL 44MQFP - Tape and Reel |
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