參數(shù)資料
型號(hào)： AD7865
廠商： Analog Devices, Inc.
英文描述： Simultaneous Sampling, Fast, 14-Bit ADC(四通道,同時(shí)采樣,高速,14位A/D轉(zhuǎn)換器)
中文描述： 同步采樣，快速，14位ADC（四通道，同時(shí)采樣，高速，14位的A / D轉(zhuǎn)換器）
文件頁(yè)數(shù)： 15/21頁(yè)
文件大?。?/td> 375K
代理商： AD7865
AD7865
Rev. PrC
–15–
Preliminary Technical Data
PRELMNARY
DATA
conversion sequence VIN1, VIN3 and VIN4 is selected
(see Selecting A Conversion Sequence) then the results of
the conversion on VIN1, VIN3 and VIN4 are placed in
registers 1 to 3 respectively. The Output Data register
pointer is reset to point to register 1 at the end of the first
conversion in the sequence, just prior to EOC going low.
At this point the logic output FRSTDATA will go logic
high to indicate that the output data register pointer is
addressing register number 1. When
CS
and
RD
are both
logic low the contents of the addressed register are
enabled onto the data bus (DB0-DB11 ).
When reading the output data registers after a conversion
sequence, i.e. when BUSY goes low, the register pointer
is incremented on the rising edge of the
RD
signal as
shown in figure 13. However when reading the conversion
results between conversions in a conversion sequence the
pointer will not be incremented until a valid conversion
result is in the register to be addressed. In this case the
pointer is incremented when the conversion has ended and
the result has been transferred to the output data register.
This happens when
EOC
goes low, therefore
EOC
may be
used to enable the register contents onto the data bus as
described in
Reading Between Conversions in the Conversion
Sequence
. The Pointer is reset to point to register 1 on the
rising edge of the
RD
signal when the last conversion
result in the sequence is being read. In the example shown
in figure 12 this means the pointer is set to register 1
when the contents of register 3 are read.
TECHNCAL
Figure 12. Output Data Registers
ec
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
0.0001
0.001
0.01
Standby Time (s)
0.1
1
10
W
-55
25
105
Fe
11. Power Up time Vs Standby Time using the On-Chip
Reference
Accessing the Output Data Registers
There are four Output Data Registers, one for each of the
four possible conversion results from a conversion se-
quence. The result of the first conversion in a conversion
sequence is placed in register 1 and the second result is
placed in register number 2 and so on. For example if the
DB0 TO DB13
O/P
DRIVERS
OE #1
NOT VALID
(V
IN3
)
(V
IN1
)
(V
IN4
)
OE #2
OE #3
OE #4
2-BIT
COUNTER
V
DRIVE
OE
RD
CS
RESET
OUTPUT DATA REGISTERS
*THE POINTER WILL NOT BE INCREMENTED BY A RISING EDGE ON RD UNTIL
IS RESET WHEN THE LAST CONVERSION RESULT IS READ
FRSTDATA
POINTER*
AD7865
D
OFFSET AND FULL-SCALE ADJUSTMENT
In most Digital Signal Processing (DSP) applications,
offset and full-scale errors have little or no effect on
system performance. Offset error can always be eliminated
effect is linear and does not cause problems as long as the
input signal is within the full dynamic range of the ADC.
Invariably, some applications will require that the input
signal to span the full analog input dynamic range. In such
applications, offset and full-scale error will have to be
adjusted to zero.
Figure 13 shows a typical circuit which can be used to
adjust the offset and full-scale errors on the AD7865 (V
A1
on the AD7865-1 version is shown for example purposes
only). Where adjustment is required, offset error must be
adjusted before full-scale error. This is achieved by
trimming the offset of the op amp driving the analog input
of the AD7865 while the input voltage is a 1/2 LSB below
analog ground. The trim procedure is as follows: apply a
voltage of –610
μ
V (–1/2 LSB) at V
and adjust the op
amp offset voltage until the ADC output code flickers
between 1111 1111 1111 and 0000 0000 0000.
Gain error can be adjusted at either the first code transi-
tion (ADC negative full scale) or the last code transition
(ADC positive full scale). The trim procedures for both
cases are as
follows:
Positive Full-Scale Adjust
Apply a voltage of +9.9982 V (FS/2 – 3/2 LSBs) at V
A1
.
Adjust R2 until the ADC output code flickers between
01 1111 1111 1110 and 01 1111 1111 1111.
Negative Full-Scale Adjust
Apply a voltage of –9.9994 V ( –FS + 1/2 LSB) at V
and
adjust R2 until the ADC output code flickers between 10
0000 0000 0000 and 10 0000 0000 0001.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD7865AS-1 制造商:Rochester Electronics LLC 功能描述:4 CH. SIMULTANEOUS BIPOLAR,14-B ADC I.C. - Bulk 制造商:Analog Devices 功能描述:Analog-Digital Converter IC Number of Bi
AD7865AS-1REEL 制造商:Analog Devices 功能描述:ADC Single SAR 350ksps 14-bit Parallel 44-Pin MQFP T/R 制造商:Rochester Electronics LLC 功能描述:4 CH. SIMULTANEOUS BIPOLAR,14-B ADC I.C. - Tape and Reel
AD7865AS2 制造商:AD 功能描述:*
AD7865AS-2 制造商:Analog Devices 功能描述:ADC Single SAR 350ksps 14-bit Parallel 44-Pin MQFP 制造商:Analog Devices 功能描述:IC 14-BIT ADC
AD7865AS-2REEL 制造商:Analog Devices 功能描述:ADC Single SAR 350ksps 14-bit Parallel 44-Pin MQFP T/R 制造商:Analog Devices 功能描述:ADC SGL SAR 350KSPS 14BIT PARALLEL 44MQFP - Tape and Reel
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