- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375240 > AD7865 (Analog Devices, Inc.) Simultaneous Sampling, Fast, 14-Bit ADC(四通道,同時(shí)采樣,高速,14位A/D轉(zhuǎn)換器) PDF資料下載
參數(shù)資料
| 型號： | AD7865 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Simultaneous Sampling, Fast, 14-Bit ADC(四通道,同時(shí)采樣,高速,14位A/D轉(zhuǎn)換器) |
| 中文描述： | 同步采樣，快速，14位ADC（四通道，同時(shí)采樣，高速，14位的A / D轉(zhuǎn)換器） |
| 文件頁數(shù)： | 13/21頁 |
| 文件大?。?/td> | 375K |
| 代理商： | AD7865 |
AD7865
Rev. PrC
–13–
Preliminary Technical Data
PRELMNARY
conversion the output data register pointer is incremented
on the rising edge of
RD
because the next conversion
result is available in this case. This means FRSTDATA
will go logic low after the first rising edge on
RD
.
Successive read operations will access the remaining
conversion results in an ascending channel order. Each
read operation increments the output data register pointer.
The read operation which accesses the last conversion
result causes the output data register pointer to be reset so
that the next read operation will access the first conversion
result again. This is shown in Figure 8 with the fifth read
after BUSY goes low accessing the result of the conver-
sion on VIN1. Thus the output data registers acts as a
circular buffer in which the conversion results may be
continually accessed. The FRSTDATA signal will go
high when the first conversion result available.
Data is enabled onto the data bus DB0 to DB13 using
CS
and
RD
. Both
CS
and
RD
have the same functionality as
described in the previous section. There are no restrictions
or performance implications associated to the position of
TECHNCAL
Reading After the Conversion Sequence
Figure 8 shows the same conversion sequence as figure 7,
however in this case the results of the four conversions (on
VIN1 to VIN4 ) are read after all conversions have
finished, i.e. when BUSY goes logic low. The
FRSTDATA signal goes logic high at the end of the first
conversion just prior to
EOC
going logic low. As men-
tioned previously FRSTDATA has an indeterminate state
after initial power up, therefore FRSTDATA may already
be logic high. Unlike the case when reading during a
the read operations after BUSY goes low, however there is
a minimum time between read operations which must be
adhered to. Notice also that a "Quiet Time" is needed
before the start of the next conversion sequence.
Using an External Clock
With the
H
/S SEL pin tied to logic 1 the AD7865 will
expect to be driven from and external clock. The highest
external clock frequency allowed is 5Mhz. This means a
conversion time of 3.2 μs compared to 2.5μs using the
internal clock. However in some instances it may be useful
to use an external clock when high throughput rates are
not required. For example two or more AD7865s may be
synchronized by using the same external clock for all
devices. In this way there is no latency between output
logic signals like
EOC
due to differences in the frequency
of the internal clock oscillators. Figure 9 shows how the
various logic outputs are synchronized to the CLK signal.
Each conversion requires 16 clocks. The output data
register pointer is reset to point to the first register
location on the falling edge of the 14th clock cycle of the
first conversion in the conversion sequence - See Access-
ing the Output Data Registers. At this point the logic
output FRSTDATA goes logic high. The result of the
first conversion is transferred to the output data registers
on the falling edge of the 14th clock cycle. The
FRSTDATA signal is reset on the falling edge of the 14th
clock cycle of the next conversion, i.e. when the result of
the second conversion is transferred to its output data
register. As mentioned previously the pointer is
incremented by the rising edge of the RD signal, however
the pointer will only be incremented if the result of the
conversion (,in this case the second conversion,) is
available. The
EOC
signal goes logic low on the falling
edge of the 14th clock cycle and is reset high again on the
falling edge of the 14 clock cycle.
Figure 8. Timing Diagram, Reading After the Conversion Sequence
t
10
t
8
t
4
t
3
t
6
t
1
QUIET
TIME
DATA
CONVST
BUSY
EOC
FRSTDATA
RD
CS
V
IN1
V
IN2
V
IN3
V
IN4
V
IN1
t
BUSY
t
2
t
10
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD7868 | Complete 12-bit I/O System Containing a DAC And an ADC(完備的12位I\O系統(tǒng)（包含一個(gè)A/D轉(zhuǎn)換器和一個(gè)D/A轉(zhuǎn)換器）) |
| AD7869 | Complete 14-bit I/O System Containing a DAC and a ADC(完備的14位I/O系統(tǒng)（包含一個(gè)A/D轉(zhuǎn)換器和一個(gè)D/A轉(zhuǎn)換器）) |
| AD7870AJN | LC2MOS Complete, 12-Bit, 100 kHz , Sampling ADC |
| AD7874AN | LC2MOS 4-Channel, 12-Bit Simultaneous Sampling Data Acquisition System |
| AD7874AQ | LC2MOS 4-Channel, 12-Bit Simultaneous Sampling Data Acquisition System |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7865AS-1 | 制造商:Rochester Electronics LLC 功能描述:4 CH. SIMULTANEOUS BIPOLAR,14-B ADC I.C. - Bulk 制造商:Analog Devices 功能描述:Analog-Digital Converter IC Number of Bi |
| AD7865AS-1REEL | 制造商:Analog Devices 功能描述:ADC Single SAR 350ksps 14-bit Parallel 44-Pin MQFP T/R 制造商:Rochester Electronics LLC 功能描述:4 CH. SIMULTANEOUS BIPOLAR,14-B ADC I.C. - Tape and Reel |
| AD7865AS2 | 制造商:AD 功能描述:* |
| AD7865AS-2 | 制造商:Analog Devices 功能描述:ADC Single SAR 350ksps 14-bit Parallel 44-Pin MQFP 制造商:Analog Devices 功能描述:IC 14-BIT ADC |
| AD7865AS-2REEL | 制造商:Analog Devices 功能描述:ADC Single SAR 350ksps 14-bit Parallel 44-Pin MQFP T/R 制造商:Analog Devices 功能描述:ADC SGL SAR 350KSPS 14BIT PARALLEL 44MQFP - Tape and Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。