- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375240 > AD7865 (Analog Devices, Inc.) Simultaneous Sampling, Fast, 14-Bit ADC(四通道,同時采樣,高速,14位A/D轉(zhuǎn)換器) PDF資料下載
參數(shù)資料
| 型號： | AD7865 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Simultaneous Sampling, Fast, 14-Bit ADC(四通道,同時采樣,高速,14位A/D轉(zhuǎn)換器) |
| 中文描述： | 同步采樣，快速，14位ADC（四通道，同時采樣，高速，14位的A / D轉(zhuǎn)換器） |
| 文件頁數(shù)： | 12/21頁 |
| 文件大小： | 375K |
| 代理商： | AD7865 |
AD7865
–12–
Rev. PrC
PRELMNARY
DATA
TECHNCAL
the first data location (i.e. first conversion result,) at the
end of the first conversion just prior to
EOC
going low.
The pointer is incremented to point to the next register
(next conversion result) by a rising edge of
RD
only
if that
conversion result is available. If a read takes place before
the next conversion is complete (as shown in figure 7)
then the pointer is incremented at the end of that conver-
sion when the
EOC
pulse goes low. Hence FRSTDATA
in figure 7 is seen to go low just after to the second
EOC
pulse. Repeated read operations during a conversion will
continue to access the data at the current pointer location
until the pointer is incremented at the end of that conver-
sion.
Note
FRSTDATA has an indeterminate logic state
after initial power up. This means that for the first conver-
sion sequence after power up, the FRSTDATA logic
output may already be logic high before the end of the
first conversion. This condition is indicated by the dashed
line in figure 8. Also the FRSTDATA logic output may
already be high as a result of the previous read sequence
as is the case after the fourth read in figure 7. The forth
read (rising edge of RD) resets the pointer to the first data
locatiocation. There FRSTDATA is already high when
the next conversion sequence is initiated. See Accessing
the Output Data Registers.
sions.
A conversion is initiated on the rising edge of
CONVST.
This
places all four track/holds into hold simultaneously.
New data from this conversion sequence is available for
the first channel selected (A
) 2.5μs later. The conver-
sion on each subsequent channel is completed at 2.5 μs
intervals. The end of each conversion is indicated by the
falling edge of the
EOC
signal. The
BUSY
output signal
indicates the end of conversion for all selected channels
(four in this case).
Data is read from the part via a 14-bit parallel data bus
with standard
CS
and
RD
signals. The
CS
and
RD
inputs
are internally gated to enable the conversion result onto
the data bus. The data lines DB0 to DB13 leave their high
impedance state when both
CS
and
RD
are logic low.
Therefore
CS
may be permanently tied logic low and the
RD
signal used to access the conversion result. Since
each conversion result is latched into its output data
register at the same time
EOC
goes logic low a further
option would be to tie the
EOC
and
RD
pins together
with
CS
tied logic low and use the rising edge of
EOC
to latch the conversion result. Although the AD7865 has
some special features which permit reading during a
conversion (,e.g. a separate supply for the output data
drivers, V
), for optimum performance it is recom-
mended that the read operation be completed when
EOC
is logic low, i.e. before the start of the next conversion.
Although figure 7 shows the read operation taking place
during the EOC pulse, a read operation can take place at
any time. Figure 7 shows a timing specification called
"Quiet Time". This is the amount of time which should be
left after a read operation and before the next conversion
is initiated. The quiet time depends heavily on data bus
capacitance but a figure of 50ns to 100ns is typical.
The signal labeled FRSTDATA (First Data Word)
indicates to the user that the pointer associated with the
output data registers is pointing to the first conversion
Figure 7. Timing Diagram for Reading During Conversion
t
CONV
t
BUSY
QUIET
TIME
t
1
t
8
t
11
t
3
t
4
t
5
t
6
t
7
V
IN1
V
IN2
V
IN3
V
IN4
100ns
100ns
DATA
CONVST
BUSY
EOC
FRSTDATA
RD
CS
H/S SEL
SL1-SL4
t
2
t
CONV
t
CONV
t
CONV
t
ACQ
t
11
t
10
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD7868 | Complete 12-bit I/O System Containing a DAC And an ADC(完備的12位I\O系統(tǒng)（包含一個A/D轉(zhuǎn)換器和一個D/A轉(zhuǎn)換器）) |
| AD7869 | Complete 14-bit I/O System Containing a DAC and a ADC(完備的14位I/O系統(tǒng)（包含一個A/D轉(zhuǎn)換器和一個D/A轉(zhuǎn)換器）) |
| AD7870AJN | LC2MOS Complete, 12-Bit, 100 kHz , Sampling ADC |
| AD7874AN | LC2MOS 4-Channel, 12-Bit Simultaneous Sampling Data Acquisition System |
| AD7874AQ | LC2MOS 4-Channel, 12-Bit Simultaneous Sampling Data Acquisition System |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7865AS-1 | 制造商:Rochester Electronics LLC 功能描述:4 CH. SIMULTANEOUS BIPOLAR,14-B ADC I.C. - Bulk 制造商:Analog Devices 功能描述:Analog-Digital Converter IC Number of Bi |
| AD7865AS-1REEL | 制造商:Analog Devices 功能描述:ADC Single SAR 350ksps 14-bit Parallel 44-Pin MQFP T/R 制造商:Rochester Electronics LLC 功能描述:4 CH. SIMULTANEOUS BIPOLAR,14-B ADC I.C. - Tape and Reel |
| AD7865AS2 | 制造商:AD 功能描述:* |
| AD7865AS-2 | 制造商:Analog Devices 功能描述:ADC Single SAR 350ksps 14-bit Parallel 44-Pin MQFP 制造商:Analog Devices 功能描述:IC 14-BIT ADC |
| AD7865AS-2REEL | 制造商:Analog Devices 功能描述:ADC Single SAR 350ksps 14-bit Parallel 44-Pin MQFP T/R 制造商:Analog Devices 功能描述:ADC SGL SAR 350KSPS 14BIT PARALLEL 44MQFP - Tape and Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。