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| 型號： | AD7865 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Simultaneous Sampling, Fast, 14-Bit ADC(四通道,同時采樣,高速,14位A/D轉(zhuǎn)換器) |
| 中文描述： | 同步采樣，快速，14位ADC（四通道，同時采樣，高速，14位的A / D轉(zhuǎn)換器） |
| 文件頁數(shù)： | 11/21頁 |
| 文件大?。?/td> | 375K |
| 代理商： | AD7865 |
AD7865
Rev. PrC
–11–
Preliminary Technical Data
PRELMNARY
1
FSR is full-scale range is 5 V, with VREF = +2.5 V.
2
1 LSB = FSR/16384 = 610.4
μ
V (±2.5 V - AD7865-3) with VREF = +2.5 V.
TECHNCAL
Figure 4. AD7865-3 Analog Input Structure
For the AD7865-3, R1 = 6 k
and R2 = 6 k
.
As a
result, the V
input should be driven from a low imped-
ance source. The resistor input stage is followed by the
high input impedance stage of the track/hold amplifier.
The designed code transitions take place midway between
successive integer LSB values (i.e., 1/2 LSB, 3/2 LSBs, 5/
2 LSBs etc.) LSB size is given by the formula, 1 LSB =
FSR/16384. Output coding is 2s complement binary with
1 LSB = FS/16384 = 5 V/16384 =610.4
μ
V. The ideal
input/output transfer function for the AD7865-3 is shown
in Table II.
TABLE II. IDEAL INPUT/OUTPUT CODE TABLE
FOR THE AD7865-3
Digital Output
Code Transition
Analog Input
l
+FSR/2 – 3/2 LSB
2
+FSR/2 – 5/2 LSBs
+FSR/2 – 7/2 LSBs
011 . . . 110 to 011 . . . 111
011 . . . 101 to 011 . . . 110
011 . . . 100 to 011 . . . 101
AGND + 3/2 LSB
AGND + 1/2 LSB
AGND – 1/2 LSB
AGND – 3/2 LSB
000 . . . 001 to 000 . . . 010
000 . . . 000 to 000 . . . 001
111 . . . 111 to 000 . . . 000
111 . . . 110 to 111 . . . 111
–FSR/2 + 5/2 LSBs
–FSR/2 + 3/2 LSBs
–FSR/2 + 1/2 LSB
100 . . . 010 to 100 . . . 011
100 . . . 001 to 100 . . . 010
100 . . . 000 to 100 . . . 001
NOTES
SELECTING A CONVERSION SEQUENCE
Any subset of the four channels VIN1 to VIN4 can be
selected for conversion. The selected channels are con-
verted in an assending order. For example if the channel
selection includes VIN4, VIN1 and VIN3 then the
conversion sequence will be VIN1, VIN3 and then VIN4.
The conversion sequenceselection my be made by using
either the hardware channel select input pins SL1 through
SL4 (if
H
/S is tied low) or programming the channel
select register (if
H
/S is tied high). A logic high on a
hardward channel select pin (or logic one in the channel
select register) when CONVST goes logic high, marks
the associated analog input channel for inclusion in the
conversion sequence.
Figure 5 shows the arrangement used. The
H
/S SEL
controls a multiplexer which select s the source of the
conversion sequence information, i.e. from the Hard-
ware channel select pins (SL1 to SL4) or from the
channel selection register. When a conversion is started
the output from the multiplexer is latched until the end of
the conversion sequence. The data bus bits DB0 to DB3
(DB0 representing channel 1 through DB3 representing
channel 4.) are bidirectional and become inputs to the
channel select register when
RD
is logic high and
CS
and
WR
are logic low. The logic state on DB0 to DB3 is
latched into the channel select register when
WR
goes
logic high. Figure 6 shows the loading sequence for
channel selection using software control.
DATA BUS
WR
CS
WR
CHANNEL SELECT
REGISTER
SL1
SL2
SL3
HARDWARE CHANNEL
SELECT PINS
H/S
TRANSPARENT WHILE WAITING FOR
CONVST. LATCHED ON THE RISING
EDGE OF CONVST AND DURING A
CONVERSION SEQUENCE.
M
U
L
T
I
P
L
E
X
E
R
LATCH
SEQUENCER
SELECT INDIVIDUAL
TRACK-AND-HOLDS
FOR CONVERSION
Figure 5. AD7865 Channel Select Inputs & Registers
RD
WR
CS
DATA
t
16
t
17
t
14
t
15
t
13
DATA IN
Figure 6. Channel Selection via Software Control
TIMING AND CONTROL
Reading Between Each Conversion in the Conversion
Sequence
Figure 7 shows the timing and control sequence required
to obtain the optimum throughput rate from the AD7865.
To obtain the optimum throughput from the AD7865 the
user must read the result of each conversion as it becomes
available. The timing diagram in figure 5 shows a read
operation each time the
EOC
signal goes logic low. The
timing in figure 7 shows a conversion on all four analog
channels (SL1 to SL4 = 1, see Selecting a Conversion
Sequence), hence there are four
EOC
pulses and four read
operations to access the result of each of the four conver-
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