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參數(shù)資料
| 型號(hào)： | AD7864 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Four Channel, Simultaneous Sampling, High Speed, 12-Bit ADC(四通道,同時(shí)采樣高速12位A/D轉(zhuǎn)換器) |
| 中文描述： | 四通道，同步采樣，高速，12位ADC（四通道，同時(shí)采樣高速12位的A / D轉(zhuǎn)換器） |
| 文件頁數(shù)： | 4/20頁 |
| 文件大小： | 394K |
| 代理商： | AD7864 |
AD7864
–4–
REV. 0
TIMING CHARACTERISTICS
1, 2
Parameter
A, B Versions
Units
μ
s max
Clock Cycles
μ
s max
μ
s max
Test Conditions/Comments
t
CONV
1.65
13
2.6
0.34
No. of Channels
x (t
CONV
+ t
9
) – t
9
2
6
35
70
Conversion Time, Internal Clock
Conversion Time, External Clock
CLKIN = 5 MHz
Acquisition Time
Selected Number of Channels Multiplied by
(t
CONV
+
EOC
Pulsewidth)—
EOC
Pulsewidth
STBY
Rising Edge to
CONVST
Rising Edge
STBY
Rising Edge to
CONVST
Rising Edge
CONVST
Pulsewidth
CONVST
Rising Edge to BUSY Rising Edge
t
ACQ
t
BUSY
μ
s max
μ
s max
ms max
ns min
ns min
t
WAKE-UP
—External V
REF
t
WAKE-UP
—Internal V
REF3
t
1
t
2
Read Operation
t
3
t
4
t
5
t
64
0
0
35
35
40
5
30
10
75
180
70
15
0
ns min
ns min
ns min
ns max
ns max
ns min
ns max
ns min
ns min
ns max
ns max
ns max
ns min
CS
to
RD
Setup Time
CS
to
RD
Hold Time
Read Pulsewidth
Data Access Time After Falling Edge of
RD
, V
DRIVE
= 5 V
Data Access Time After Falling Edge of
RD
, V
DRIVE
= 3 V
Bus Relinquish Time After Rising Edge of
RD
t
75
t
8
t
9
Time Between Consecutive Reads
EOC
Pulsewidth
t
10
t
11
t
12
Write Operation
t
13
t
14
t
15
t
16
t
17
RD
Rising Edge to FRSTDATA Edge (Rising or Falling)
EOC
Falling Edge to FRSTDATA Falling Delay
EOC
to
RD
Delay
20
0
0
5
5
ns min
ns min
ns min
ns min
ns min
WR
Pulsewidth
CS
to
WR
Setup Time
WR
to
CS
Hold Time
Input Data Setup Time of Rising Edge of
WR
Input Data Hold Time
NOTES
1
Sample tested at +25
°
C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of +5 V) and timed from a voltage level of +1.6V.
2
See Figures 7, 8 and 9.
3
Refer to the section, “Standby Mode Operation.” The MAX specification of 6 ms is valid when using a 0.1
μ
F decoupling capacitor on the V
REF
pin.
4
Measured with the load circuit of Figure 2 and defined as the time required for an output to cross 0.8V or 2.4 V.
5
These times are derived from the measured time taken by the data outputs to change 0.5V when loaded with the circuit of Figure 2. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
Specifications subject to change without notice.
(V
D
= +5 V
6
5%, AGND = DGND= 0 V, V
REF
= Internal, Clock = Internal; all specifications
T
MIN
to T
MAX
unless otherwise noted)
TO
OUTPUT
50pF
1
1.6V
400
m
A
1.6mA
Figure 1. Load Circuit for Access Time and Bus Relinquish Time
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| AD7864_09 | 制造商:AD 制造商全稱:Analog Devices 功能描述:4-Channel, Simultaneous Sampling, High Speed, 12-Bit ADC |
| AD7864AS | 制造商:AD 制造商全稱:Analog Devices 功能描述:IC-SM-12-BIT ADC |
| AD7864AS-1 | 制造商:Analog Devices 功能描述: 制造商:Analog Devices 功能描述:IC 12BIT ADC SMD 7864 LQFP44 |
| AD7864AS-2 | 制造商:Analog Devices 功能描述:ADC Single SAR 520ksps 12-bit Parallel 44-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:4 CH.SIMULTANEOUS SAMPL.500 KSPS ADC I.C - Bulk 制造商:Analog Devices 功能描述:IC 12-BIT ADC |
| AD7864AS-2REEL | 制造商:Analog Devices 功能描述:ADC Single SAR 520ksps 12-bit Parallel 44-Pin MQFP T/R |
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