參數(shù)資料
型號： AD7837
廠商： Analog Devices, Inc.
英文描述： Complete, Dual 12-Bit MDACs(完備的雙12位乘法D/A轉(zhuǎn)換器)
中文描述： 完備的雙12位醫(yī)療儀器行政管理制度（完備的雙12位乘法的D / A轉(zhuǎn)換器）
文件頁數(shù)： 8/12頁
文件大?。?/td> 280K
代理商： AD7837
AD7837/AD7847
REV. 0
–8–
ADDRESS VALID
A0/A1
CS
t
1
WR
DATA
VALID
DATA
LDAC
t
6
t
7
t
3
t
2
t
4
t
5
t
8
Figure 5. AD7837 Write Cycle Timing Diagram
CS
,
WR
, A0 and A1 control the loading of data to the input
latches. T he eight data inputs accept right-justified data. Data
can be loaded to the input latches in any sequence. Provided
that
LDAC
is held high, there is no analog output change as a
result of loading data to the input latches. Address lines A0 and
A1 determine which latch data is loaded to when
CS
and
WR
are low. T he control logic truth table for the part is shown in
T able II.
T able II. AD7837 T ruth T able
CS WR
A1 A0
LDAC
Function
1
X
0
0
0
0
1
X
1
0
0
0
0
1
X
X
0
0
1
1
X
X
X
0
1
0
1
X
1
1
1
1
1
1
0
No Data T ransfer
No Data T ransfer
DAC A LS Input Latch T ransparent
DAC A MS Input Latch T ransparent
DAC B LS Input Latch T ransparent
DAC B MS Input Latch T ransparent
DAC A and DAC B DAC Latches
Updated Simultaneously from the
Respective Input Latches
X = Don’t Care.
T he
LDAC
input controls the transfer of 12-bit data from the
input latches to the DAC latches. When
LDAC
is taken low,
both DAC latches, and hence both analog outputs, are updated
at the same time. T he data in the DAC latches is held on the
rising edge of
LDAC
. T he
LDAC
input is asynchronous and in-
dependent of
WR
. T his is useful in many applications especially
in the simultaneous updating of multiple AD7837s. However,
care must be taken while exercising
LDAC
during a write cycle.
If an
LDAC
operation overlaps a
CS
and
WR
operation, there
is a possibility of invalid data being latched to the output. T o
avoid this,
LDAC
must remain low after
CS
or
WR
return high
for a period equal to or greater than t
8
, the minimum
LDAC
pulse width.
UNIPOLAR BINARY OPE RAT ION
Figure 6 shows DAC A on the AD7837/AD7847 connected for
unipolar binary operation. Similar connections apply for DAC
B. When V
IN
is an ac signal, the circuit performs 2-quadrant
multiplication. T he code table for this circuit is shown in
T able III. Note that on the AD7847 the feedback resistor R
FB
is
internally connected to V
OUT
.
DAC A
V
SS
*
AGNDA
DGND
*
INTERNALLY
CONNECTED
ON AD7847
AD7837
AD7847
V
SS
V
OUTA
V
OUT
R
FBA
V
DD
V
REFA
V
DD
V
IN
Figure 6. Unipolar Binary Operation
T able III. Unipolar Code T able
DAC Latch Contents
MSB LSB
Analog Output, V
OUT
1111 1111 1111
±
V
IN
×
4095
4096
1000 0000 0000
±
V
IN
×
2048
4096
=
±1/2
V
IN
0000 0000 0001
0 V
±
V
IN
×
1
4096
0000 0000 0000
Note 1 LSB =
V
IN
4096
.
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