參數(shù)資料
型號(hào)： AD7837
廠商： Analog Devices, Inc.
英文描述： Complete, Dual 12-Bit MDACs(完備的雙12位乘法D/A轉(zhuǎn)換器)
中文描述： 完備的雙12位醫(yī)療儀器行政管理制度（完備的雙12位乘法的D / A轉(zhuǎn)換器）
文件頁(yè)數(shù)： 2/12頁(yè)
文件大?。?/td> 280K
代理商： AD7837
REV. 0
–2–
AD7837/AD7847–SPECIFICATIONS
1
(V
DD
= +15 V
6
5%, V
SS
= –15 V
6
5%, AGNDA = AGNDB = DGND
= OV. V
REFA
= V
REFB
= +10 V, R
L
= 2 k
V
, C
L
= 100 pF [V
OUT
connected to R
FB
AD7837]. All specifications T
MN
to T
MAX
unless otherwse noted.)
Parameter
A Version
B Version
S Version
Units
T est Conditions/Comments
ST AT IC PERFORMANCE
Resolution
Relative Accuracy
2
Differential Nonlinearity
2
Zero Code Offset Error
2
@ +25
°
C
T
MIN
to T
MAX
Gain Error
2
@ +25
°
C
T
MIN
to T
MAX
12
±
1
±
1
12
±
1/2
±
1
12
±
1
±
1
Bits
LSB max
LSB max
Guaranteed Monotonic
±
2
±
4
±
2
±
3
±
2
±
5
mV max
mV max
DAC Latch Loaded with All 0s
T emperature Coefficient =
±
5
μ
V/
°
C typ
±
5
±
7
±
2
±
4
±
5
±
7
LSB max
LSB max
DAC Latch Loaded with All 1s
T emperature Coefficient =
±
2 ppm of
FSR/
°
C typ
REFERENCE INPUT S
V
REF
Input Resistance
V
REFA
, V
REFB
Resistance Matching
8/13
±
3
8/13
±
3
8/13
±
3
k
min/max
% max
T ypical Input Resistance = 10 k
T ypically
±
0.5%
DIGIT AL INPUT S
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current
Input Capacitance
3
2.4
0.8
±
1
8
2.4
0.8
±
1
8
2.4
0.8
±
1
8
V min
V max
μ
A max
pF max
Digital Inputs at 0 V and V
DD
ANALOG OUT PUT S
DC Output Impedance
Short Circuit Current
0.2
15
0.2
15
0.2
15
typ
mA typ
V
OUT
Connected to AGND
POWER REQUIREMENT S
4
V
DD
Range
V
SS
Range
Power Supply Rejection
Gain/
V
DD
Gain/
V
SS
I
DD
I
SS
14.25/15.75
–14.25/–15.75
14.25/15.75
–14.25/–15.75 –14.25/–15.75
14.25/15.75
V min/max
V min/max
±
0.1
±
0.1
10
6
±
0.1
±
0.1
10
6
±
0.1
±
0.1
10
6
% per % max
% per % max
mA max
mA max
V
DD
= 15 V
±
5%, V
REF
= –10 V
V
SS
= –15 V
±
5%, V
REF
= +10 V
Output Unloaded. T ypically 5 mA
Output Unloaded. T ypically 4 mA
AC CHARACT ERIST ICS
2, 3
Voltage Output Settling T ime
4
4
4
μ
s typ
Settling T ime to Within
±
1/2 LSB of Final
Value. DAC Latch Alternately Loaded
with All 0s and All 1s
Slew Rate
Digital-to-Analog Glitch Impulse
7
175
7
175
7
175
V/
μ
s typ
nV secs typ
DAC Latch Alternately Loaded with
01 . . . 11 and 10 . . . 00
Channel-to-Channel Isolation
V
REFA
to V
OUT B
–95
–95
–95
dB typ
V
REFA
= 20 V p-p, 10 kHz Sine Wave.
DAC Latches Loaded with All 0s
V
REFB
= 20 V p-p, 10 kHz Sine Wave.
DAC Latches Loaded with All 0s
V
REF
= 20 V p-p, 10 kHz Sine Wave.
DAC Latch Loaded with All 0s
V
REF
= 100 mV p-p Sine Wave. DAC
Latch Loaded with All 1s
V
REF
= 20 V p-p Sine Wave. DAC
Latch Loaded with All 1s
V
REF
= 6 V rms, 1 kHz. DAC Latch
Loaded with All 1s
Code T ransition from All 0s to All 1s
See T ypical Performance Graphs
Amplifier Noise and Johnson Noise of R
FB
V
REFB
to V
OUT A
–95
–95
–95
dB typ
Multiplying Feedthrough Error
–90
–90
–90
dB typ
Unity Gain Small Signal BW
600
600
600
kHz typ
Full Power BW
110
110
90
kHz typ
T otal Harmonic Distortion
–88
–88
–88
dB typ
Digital Crosstalk
Output Noise Voltage @ +25
°
C
(0.1 Hz to 10 Hz)
10
10
10
nV secs typ
2
2
2
μ
V rms typ
NOT ES
1
T emperature ranges are as follows: A, B Versions, –40
°
C to +85
°
C; S Version, –55
°
C to +125
°
C.
2
See T erminology.
3
Sample tested @ +25
°
C to ensure compliance.
4
T he Devices are functional with V
DD
/V
SS
=
±
12 V (See typical performance graphs.)
Specifications subject to change without notice.
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