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參數(shù)資料
| 型號： | AD7837 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Complete, Dual 12-Bit MDACs(完備的雙12位乘法D/A轉(zhuǎn)換器) |
| 中文描述： | 完備的雙12位醫(yī)療儀器行政管理制度（完備的雙12位乘法的D / A轉(zhuǎn)換器） |
| 文件頁數(shù)： | 11/12頁 |
| 文件大小： | 280K |
| 代理商： | AD7837 |
AD7837/AD7847
REV. 0
–11–
ADDRESS BUS
ADDR
DECODE
CSA
CSB
16-BIT
LATCH
WR
DB11
DB0
ADDRESS/DATA BUS
AD7847*
*ADDITIONAL PINS OMITTED FOR CLARITY
ALE
WR
AD15
AD0
8086
Figure 11. AD7847 to 8086 Interface
AD7847–MC68000 Interface
Figure 12 shows an interface between the AD7847 and the
MC68000. Once again a single MOVE instruction loads the
12-bit word into the selected DAC latch.
CSA
and
CSB
are AND-
gated to provide a
DTACK
signal when either DAC latch is
selected.
ADDRESS BUS
CSA
CSB
WR
DB11
DB0
DATA BUS
AD7847*
*
ADDITIONAL PINS OMITTED FOR CLARITY
D15
D0
MC68000
ADDR
DECODE
EN
A23
A1
DTACK
LDS
R/W
AS
Figure 12. AD7847 to MC68000 Interface
AD7847–T MS320C10 Interface
Figure 13 shows an interface between the AD7847 and the
T MS320C10 DSP processor. A single OUT instruction loads
the 12-bit word into the selected DAC latch.
ADDRESS BUS
CSA
CSB
WR
DB11
DB0
DATA BUS
AD7847*
*
ADDITIONAL PINS OMITTED FOR CLARITY
D15
D0
TMS320C10
ADDR
DECODE
EN
A11
A0
MEN
WE
Figure 13. AD7847 to TMS320C10 Interface
MICROPROCE SSOR INT E RFACING–AD7837
Figures 14 to 16 show the AD7837 configured for interfacing to
microprocessors with 8-bit data bus systems. In all cases, data is
right-justified and the AD7837 is memory-mapped with the two
lowest address lines of the microprocessor address bus driving
the A0 and A1 inputs of the AD7837. Five separate memory ad-
dresses are required, one for the each MS latch and one for each
LS latch and one for the common
LDAC
input. Data is written
to the respective input latch in two write operations. Either high
byte or low byte data can be written first to the input latch. A
write to the AD7837
LDAC
address transfers the data from the
input latches to the respective DAC latches and updates both
analog outputs. Alternatively, the
LDAC
input can be asynchro-
nous and can be common to a several AD7837s for simulta-
neous updating of a number of voltage channels.
AD7837–8051/8088 Interface
Figure 14 shows the connection diagram for interfacing the
AD7837 to both the 8051 and the 8088. On the 8051, the
signal
PSEN
is used to enable the address decoder while
DEN
is used on the 8088.
ADDRESS BUS
ADDR
DECODE
OCTAL
LATCH
WR
DB7
DB0
ADDRESS/DATA BUS
AD7837*
*
ADDITIONAL PINS OMITTED FOR CLARITY
ALE
WR
AD7
AD0
8051/8088
A0
A1
EN
PSEN OR DEN
CS
LDAC
A15
A8
Figure 14. AD7837 to 8051/8088 Interface
AD7837–68008 Interface
An interface between the AD7837 and the MC68008 is shown
in Figure 15. In the diagram shown, the
LDAC
signal is derived
from an asynchronous timer but this can be derived from the
address decoder as in the previous interface diagram.
ADDRESS BUS
WR
DB7
DB0
DATA BUS
AD7837*
*
ADDITIONAL PINS OMITTED FOR CLARITY
D7
D0
MC68008
ADDR
DECODE
EN
A19
A0
DTACK
DS
R/W
AS
CS
LDAC
TIMER
A0
A1
Figure 15. AD7837 to 68008 Interface
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7837AN | 功能描述:IC DAC 12BIT MULT DUAL 24-DIP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標(biāo)準(zhǔn)包裝:750 系列:- 設(shè)置時間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
| AD7837AN/883B | 制造商:AD 制造商全稱:Analog Devices 功能描述:LC2MOS Complete, Dual 12-Bit MDACs |
| AD7837AN883B | 制造商:AD 制造商全稱:Analog Devices 功能描述:LC2MOS Complete, Dual 12-Bit MDACs |
| AD7837AN-883B | 制造商:AD 制造商全稱:Analog Devices 功能描述:LC2MOS Complete, Dual 12-Bit MDACs |
| AD7837ANN | 制造商:AD 制造商全稱:Analog Devices 功能描述:LC2MOS Complete, Dual 12-Bit MDACs |
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