參數(shù)資料
型號: AD7837
廠商: Analog Devices, Inc.
英文描述: Complete, Dual 12-Bit MDACs(完備的雙12位乘法D/A轉(zhuǎn)換器)
中文描述: 完備的雙12位醫(yī)療儀器行政管理制度(完備的雙12位乘法的D / A轉(zhuǎn)換器)
文件頁數(shù): 10/12頁
文件大小: 280K
代理商: AD7837
AD7837/AD7847
REV. 0
–10–
ANALOG PANNING CIRCUIT
In audio applications it is often necessary to digitally “pan” or
split a single signal source into a two-channel signal while main-
taining the total power delivered to both channels constant. T his
may be done very simply by feeding the signal into the V
REF
in-
put of both DACs. T he digital codes are chosen such that the
code applied to DAC B is the 2s complement of that applied to
DAC A. In this way the signal may be panned between both
channels as the digital code is changed. T he total power varia-
tion with this arrangement is 3 dB.
For applications which require more precise power control the
circuit shown in Figure 9 may be used. T his circuit
requires the
AD7837/AD7847, an AD712 dual op amp and 8 equal value
resistors.
Again both channels are driven with 2s complementary data.
T he maximum power variation using this circuit is only 0.5 dBs.
1/2 AD712
1/2 AD712
R
R
R
R
R
R
R
R
V
IN
V
OUTA
V
OUTB
RL
B
RL
A
V
REFA
V
OUTA
V
OUTB
V
REFB
AD7847
Figure 9. Analog Panning Circuit
T he voltage output expressions for the two channels are as
follows:
V
OUTA
=
±
V
IN
N
A
2
12
+
N
A
V
OUT B
=
±
V
IN
N
B
2
12
+
N
B
where
N
A
= DAC A input code in decimal (1
N
A
4095)
and
N
B
= DAC B input code in decimal (1
N
B
4095)
with
N
B
= 2s complement of N
A
.
T he 2s complement relationship between N
A
and N
B
causes N
B
to increase as N
A
decreases and vice versa.
Hence
N
A
+
N
B
= 4096.
With
N
A
= 2048, then
N
B
= 2048 also; this gives the balanced
condition where the power is split equally between both chan-
nels. T he total power variation as the signal is fully panned from
Channel B to Channel A is shown in Figure 10.
0.6
0.5
0.4
0.3
0.2
0.1
0.0
1
512
1024
1536
2048
2560
3072
3584
4095
T
DIGITAL INPUT CODE N
A
Figure 10. Power Variation for Circuit in Figure 9
APPLY ING T HE AD7837/AD7847
General Ground Management
AC or transient voltages between the analog and digital grounds
i.e., between AGNDA/AGNDB and DGND can cause noise in-
jection into the analog output. T he best method of ensuring that
both AGNDs and DGND are equal is to connect them together
at the AD7837/AD7847 on the circuit board. In more complex
systems where the AGND and DGND intertie is on the back-
plane, it is recommended that two diodes be connected in in-
verse parallel between the AGND and DGND pins (1N914 or
equivalent).
Power Supply Decoupling
In order to minimize noise it is recommended that the V
DD
and
the V
SS
lines on the AD7837/AD7847 be decoupled to DGND
using a 10
μ
F in parallel with a 0.1
μ
F ceramic capacitor.
Operation with Reduced Power Supply Voltages
T he AD7837/AD7847 is specified for operation with V
DD
/V
SS
=
±
15 V
±
5%. T he part may be operated down to V
DD
/V
SS
=
±
10 V without significant linearity degradation. See typical per-
formance graphs. T he output amplifier however requires ap-
proximately 3 V of headroom so the V
REF
input should not
approach within 3 V of either power supply voltages in order to
maintain accuracy.
MICROPROCE SSOR INT E RFACING–AD7847
Figures 11 to 13 show interfaces between the AD7847 and three
popular 16-bit microprocessor systems, the 8086, MC68000
and the T MS320C10. In all interfaces, the AD7847 is memory-
mapped with a separate memory address for each DAC latch.
AD7847–8086 Interface
Figure 11 shows an interface between the AD7847 and the 8086
microprocessor. A single MOV instruction loads the 12-bit word
into the selected DAC latch and the output responds on the ris-
ing edge of
WR
.
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