- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375239 > AD7836AS (ANALOG DEVICES INC) LC2MOS Quad 14-Bit DAC PDF資料下載
參數(shù)資料
| 型號(hào)： | AD7836AS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | LC2MOS Quad 14-Bit DAC |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 16 us SETTLING TIME, 14-BIT DAC, PQFP44 |
| 封裝： | PLASTIC, MQFP-44 |
| 文件頁數(shù)： | 9/12頁 |
| 文件大小： | 174K |
| 代理商： | AD7836AS |
AD7836
–
9
–
REV. A
Power-On with
CLR
Low
The output stage of the AD7836 has been designed to allow
output stability during power-on. If
CLR
is kept low during
power-on, then just after power is applied to the AD7836, the
situation is as depicted in Figure 14. G
1
, G
4
and G
6
are open
while G
2
, G
3
and G
5
are closed.
DAC
G
1
G
3
V
OUT
6k
G
6
G
4
G
5
G
2
DUTGND
R
R
Figure 14. Output Stage with V
DD
< 10 V
V
OUT
is kept within a few hundred millivolts of DUTGND via
G
5
and a 6k
resistor. This thin-film resistor is connected in
parallel with the gain resistors of the output amplifier. The out-
put amplifier is connected as a unity gain buffer via G
3
, and the
DUTGND voltage is applied to the buffer input via G
2
. The
amplifier’s output is thus at the same voltage as the DUTGND
pin. The output stage remains configured as in Figure 14 until
the voltage at V
DD
and V
SS
reaches approximately
±
10 V. By
now the output amplifier has enough headroom to handle sig-
nals at its input and has also had time to settle. The internal
power-on circuitry opens G
3
and G
5
and closes G
4
and G
6
. This
situation is shown in Figure 15. Now the output amplifier is
configured in its noise gain configuration via G
4
and G
6
. The
DUTGND voltage is still connected to the noninverting input
via G2 and this voltage appears at V
OUT
.
DAC
G
1
G
3
V
OUT
6k
G
6
G
4
G
5
G
2
DUTGND
R
R
Figure 15. Output Stage with V
DD
> 10 V and
CLR
Low
V
OUT
has been disconnected from the DUTGND pin by the
opening of G
5
but will track the voltage present at DUTGND
via the configuration shown in Figure 15.
When
CLR
is taken back high, the output stage is configured as
shown in Figure 16. The internal control logic closes G
1
and
opens G
2
. The output amplifier is connected in a noninverting
gain of two configuration. The voltage that appears on the Vout
pins is determined by the data present in the DAC registers. To
set all output voltages to the same known state, a write to
DATA REG E with the SEL pin high allows all DAC registers
to be updated with the same data.
DAC
G
1
G
3
V
OUT
6k
G
6
G
4
G
5
G
2
DUTGND
R
R
Figure 16. Output Stage After
CLR
Is Taken High
Power-On with
CLR
High
If
CLR
is high on the application of power to the device, the
output stages of the AD7836 are configured as in Figure 17
while V
DD
/V
SS
are less than
±
10 V. G
1
is closed and G
2
is open
thereby connecting the output of the DAC to the input of its
output amplifier. G
3
and G
5
are closed while G
4
and G
6
are
open thus connecting the output amplifier as a unity gain
buffer. V
OUT
is connected to DUTGND via G
5
through a 6 k
resistor until V
DD
and V
SS
reach approximately
±
10 V.
DAC
G
1
G
3
V
OUT
6k
G
6
G
4
G
5
G
2
DUTGND
R
R
Figure 17. Output Stage Powering Up with
CLR
High
While V
DD
/V
SS
<
±
10 V
When the supplies reach
±
10 V, the internal power on circuitry
opens G
3
and G
5
and closes G
4
and G
6
configuring the output
stage as shown in Figure 18.
DAC
G
1
G
3
V
OUT
6k
G
6
G
4
G
5
G
2
DUTGND
R
R
Figure 18. Output Stage Powering Up with
CLR
High
When V
DD
/V
SS
>
±
10 V
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD7836 | Quad 14-Bit DAC(14位四通道D/A轉(zhuǎn)換器) |
| AD7837 | Complete, Dual 12-Bit MDACs(完備的雙12位乘法D/A轉(zhuǎn)換器) |
| AD7838 | Octal, 13-Bit Voltage-Output DAC with Parallel Interface(并行接口,8通道13位電壓輸出D/A轉(zhuǎn)換器) |
| AD7855 | 3 V to 5 V Single Supply, 600 kSPS 12-Bit Sampling ADCs(單電源,600kSPS12位采樣A/D轉(zhuǎn)換器) |
| AD7856AN | 5 V Single Supply, 8-Channel 14-Bit 285 kSPS Sampling ADC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7836ASZ | 功能描述:IC DAC 14BIT QUAD LC2MOS 44MQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1,000 系列:- 設(shè)置時(shí)間:1µs 位數(shù):8 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:8 電壓電源:雙 ± 功率耗散（最大）:941mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC W 包裝:帶卷 (TR) 輸出數(shù)目和類型:8 電壓，單極 采樣率（每秒）:* |
| AD7837 | 制造商:AD 制造商全稱:Analog Devices 功能描述:LC2MOS Complete, Dual 12-Bit MDACs |
| AD7837AN | 功能描述:IC DAC 12BIT MULT DUAL 24-DIP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標(biāo)準(zhǔn)包裝:750 系列:- 設(shè)置時(shí)間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
| AD7837AN/883B | 制造商:AD 制造商全稱:Analog Devices 功能描述:LC2MOS Complete, Dual 12-Bit MDACs |
| AD7837AN883B | 制造商:AD 制造商全稱:Analog Devices 功能描述:LC2MOS Complete, Dual 12-Bit MDACs |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。