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參數(shù)資料
| 型號(hào)： | AD7836AS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | LC2MOS Quad 14-Bit DAC |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 16 us SETTLING TIME, 14-BIT DAC, PQFP44 |
| 封裝： | PLASTIC, MQFP-44 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 174K |
| 代理商： | AD7836AS |
AD7836
–
5
–
REV. A
PIN DESCRIPTION
Pin Mnemonic
Description
V
CC
V
SS
V
DD
DGND
AGND
V
REF
(+)A, V
REF
(–)A
V
REF
(+)B, V
REF
(–)B
V
REF
(+)C, V
REF
(–)C
V
REF
(+)D, V
REF
(–)D
V
OUT
A . . . V
OUT
D
CS
DB0 . . . DB13
Logic Power Supply; +5 V
±
5%.
Negative Analog Power Supply; –15 V
±
5%.
Positive Analog Power Supply; +15 V
±
5%.
Digital Ground.
Analog Ground.
Reference Inputs for DAC A. These reference voltages are referred to AGND.
Reference Inputs for DAC B. These reference voltages are referred to AGND.
Reference Inputs for DAC C. These reference voltages are referred to AGND.
Reference Inputs for DAC D. These reference voltages are referred to AGND.
DAC Outputs.
Level-Triggered Chip Select Input (active low). The device is selected when this input is low.
Parallel Data Inputs. The AD7836 can accept a straight 14-bit parallel word on DB0 to DB13 where
DB13 is the MSB and DB0 is the LSB.
Address inputs. A0, A1 and A2 are decoded to select one of the five input latches for a data transfer.
Asynchronous Clear Input (level sensitive, active low). When this input is low, all analog outputs are
switched to the externally set potential on the DUTGND pin. The contents of data registers A to E are
not affected when the
CLR
pin is taken low. When
CLR
is brought back high, the DAC outputs revert
back to their original outputs as determined by the data in their data registers.
Level-Triggered Write Input (active low), when active and used in conjunction with
CS
to write data to
the AD7836 input buffer. Data is latched into the selected data register on the rising edge of
WR
.
Device Sense Ground for DAC A. Vout A is referenced to the voltage applied to this pin.
Device Sense Ground for DAC B. Vout B is referenced to the voltage applied to this pin.
Device Sense Ground for DAC C. Vout C is referenced to the voltage applied to this pin.
Device Sense Ground for DAC D. Vout D is referenced to the voltage applied to this pin.
Select pin, active high level triggered input. When the SEL input is high, the user programmed value in
DATAREG E will be loaded into all DAC registers and the DAC outputs updated accordingly. The con-
tents of the other DATA REGs (A–D) will not be affected by the SEL pin.
A0, A1, A2
CLR
WR
DUTGND A
DUTGND B
DUTGND C
DUTGND D
SEL
PIN CONFIGURATION
12
13
14
15
16
17
18
19
21
PIN 1
TOP VIEW
(Not to Scale)
AD7836
NC = NO CONNECT
20
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
1
2
3
4
5
6
7
8
9
10 11
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DGND
V
CC
CLR
V
OUT
C
V
REF
(
–
)C
V
REF
(+)C
AGND
NC
V
DD
NC
V
SS
V
REF
(+)A
V
REF
(
–
)A
V
OUT
A
D
V
R
(
V
R
(
–
)
V
O
D
D
D
D
D
D
D
D
D
V
R
(
V
R
(
–
)
V
O
B
D
A
A
A
S
C
W
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