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參數(shù)資料
| 型號(hào)： | AD7824 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | High Speed 4-Channel 8-Bit ADC(四通道LC2MOS高速8位A/D轉(zhuǎn)換器) |
| 中文描述： | 高速4通道8位ADC（四通道LC2MOS高速8位的A / D轉(zhuǎn)換器） |
| 文件頁數(shù)： | 9/12頁 |
| 文件大小： | 273K |
| 代理商： | AD7824 |
AD7824/AD7828
REV. C
–9–
MODE 0
Figure 14 shows the timing diagram for Mode 0 operation. T his
mode can only be used for microprocessors which have a WAIT
state facility, whereby a READ instruction cycle can be ex-
tended to accommodate slow memory devices. A READ opera-
tion brings
CS
and
RD
low which starts a conversion. T he analog
multiplexer address inputs must remain valid while
CS
and
RD
are low. T he data bus (DB7–DB0) remains in the three-state
condition until conversion is complete. T here are two converter
status outputs on the AD7824/AD7828, interrupt (
INT
) and
ready (RDY) which can be used to drive the microprocessor
READY/WAIT input. T he RDY is an open drain output (no in-
ternal pull-up device) which goes low on the falling edge of
CS
and goes high impedance at the end of conversion, when the
8-bit conversion result appears on the data outputs. If the RDY
status is not required, then the external pull-up resistor can be
omitted and the RDY output tied to GND. T he
INT
goes low
when conversion is complete and returns high on the rising edge
of
CS
or
RD
.
MODE 1
Mode 1 operation is designed for applications where the micro-
processor is not forced into a WAIT state. A READ operation
takes
CS
and
RD
low which triggers a conversion (see Figure
15). T he multiplexer address inputs are latched on the rising
edge of
RD
. Data from the previous conversion is read from the
three-state data outputs (DB7–DB0). T his data may be disre-
garded if not required. Note, the RDY output (open drain out-
put) does not provide any status information in this mode and
must be connected to GND. At the end of conversion
INT
goes low. A second READ operation is required to access the
new conversion result. T his READ operation latches a new ad-
dress into the multiplexer inputs and starts another conversion.
INT
returns high at the end of the second READ operation,
when
CS
or
RD
returns high. A delay of 2.5
μ
s must be allowed
between READ operations.
Figure 14. Mode 0 Timing Diagram
Figure 15. Mode 1 Timing Diagram
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| AD7824BCHIPS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single-Ended Data Acquisition System |
| AD7824BQ | 功能描述:IC ADC 8BIT LC2MOS 4CH HS 24CDIP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個(gè)單端，單極；2 個(gè)差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| AD7824BQ/+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single-Ended Data Acquisition System |
| AD7824CQ | 功能描述:IC ADC 8BIT LC2MOS 4CH HS 24CDIP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個(gè)單端，雙極 |
| AD7824CQ/+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single-Ended Data Acquisition System |
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