參數(shù)資料
型號: AD7824
廠商: Analog Devices, Inc.
英文描述: High Speed 4-Channel 8-Bit ADC(四通道LC2MOS高速8位A/D轉(zhuǎn)換器)
中文描述: 高速4通道8位ADC(四通道LC2MOS高速8位的A / D轉(zhuǎn)換器)
文件頁數(shù): 3/12頁
文件大小: 273K
代理商: AD7824
AD7824/AD7828
REV. C
–3–
TIMNGCHARACTERISTICS
1
(V
DD
= +5 V; V
REF
(+) = +5 V; V
REF
(–) = GND = 0 V unless otherwse noted)
Limit at
T
MIN
, T
MAX
(K, L, B, C Grades)
Limit at
T
MIN
, T
MAX
(T , U Grades)
Limit at +25
8
C
(All Grades)
Parameter
Units
Conditions/Comments
t
CSS
t
CSH
t
AS
t
AH
t
RDY2
0
0
0
30
40
0
0
0
35
60
0
0
0
40
60
ns min
ns min
ns min
ns min
ns max
CS
to
RD
Setup T ime
CS
to
RD
Hold T ime
Multiplexer Address Setup T ime
Multiplexer Address Hold T ime
CS
to RDY Delay. Pull-Up
Resistor 5 k
.
Conversion T ime, Mode 0
Data Access T ime after
RD
Data Access T ime after
INT
, Mode 0
RD
to
INT
Delay
t
CRD
t
ACC13
t
ACC23
t
lNT H2
2.0
85
50
40
75
60
500
60
600
2.4
110
60
65
100
70
500
80
500
2.8
120
70
70
100
70
600
80
400
μ
s max
ns max
ns max
ns typ
ns max
ns max
ns min
ns min
ns max
t
DH4
t
P
t
RD
Data Hold T ime
Delay T ime between Conversions
Read Pulse Width, Mode 1
NOT ES
1
Sample tested at +25
°
C to ensure compliance. All input control signals are specified with tr = tf = 20 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
2
C
L
= 50 pF.
3
Measured with load circuits of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
4
Defined as the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 2.
Specifications subject to change without notice.
Test Circuits
Figure 1. Load Circuits for Data Access Time Test
Figure 2. Load Circuits for Data Hold Time Test
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