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參數(shù)資料
| 型號(hào)： | AD7824 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | High Speed 4-Channel 8-Bit ADC(四通道LC2MOS高速8位A/D轉(zhuǎn)換器) |
| 中文描述： | 高速4通道8位ADC（四通道LC2MOS高速8位的A / D轉(zhuǎn)換器） |
| 文件頁(yè)數(shù)： | 10/12頁(yè) |
| 文件大?。?/td> | 273K |
| 代理商： | AD7824 |
AD7824/AD7828
REV. C
–10–
MICROPROCE SSOR INT E RFACING
T he AD7824/AD7828 is designed to interface to microproces-
sors as Read Only Memory (ROM). Analog channel selection,
conversion start and data read operations are controlled by
CS
,
RD
and the channel address inputs. T hese signals are common
to all memory peripheral devices.
Z80 MICROPROCE SSOR
Figure 16 shows a typical AD7824/AD7828–Z80 interface. T he
AD7824/AD7828 is operating in Mode 0. Assume the ADC is
assigned a memory block starting at address C000. T he follow-
ing LOAD instruction to any of the addresses listed in T able II
will start a conversion of the selected channel and read the con-
version result.
LD B, (C000)
At the beginning of the instruction cycle when the ADC ad-
dress is selected, RDY asserts the WAIT input, so that the Z80
is forced into a WAIT state. At the end of conversion RDY re-
turns high and the conversion result is placed in the B register
of the microprocessor.
Figure 16. AD7824/AD7828–Z80 lnterface
T able II. Address Channel Selection
AD7824
Channel
AD7828
Channel
Address
C000
C001
C002
C003
C004
C005
C006
C007
1
2
3
4
1
2
3
4
5
6
7
8
MC68000 MICROPROCE SSOR
Figure 17 shows a MC68000 interface. T he AD7824/AD7828
is operating in Mode 0. Assume the ADC is again assigned a
memory block starting at address C000. A MOVE instruction
to any of the addresses in T able II starts a conversion and reads
the conversion result.
MOVEB $C000,D0
Once conversion has begun, the MC68000 inserts WAIT states,
until INT goes low asserting DT ACK at the end of conversion.
T he microprocessor then places the conversion results in the
D0 register.
Figure 17. AD7824/AD7828–MC68000 Interface
T MS32010 MICROCOMPUT E R
A T MS32010 interface is shown in Figure 18. T he AD7824/
AD7828 is operating in Mode 1 (i.e., no
μ
P WAIT states). T he
ADC is mapped at a port address. T he following I/O instruction
starts a conversion and reads the previous conversion result into
the accumulator.
IN, A PA (PA = PORT ADDRESS)
T he port address (000 to 111) selects the analog channel to be
converted. When conversion is complete a second I/O instruc-
tion (IN, A PA) reads the up-to-date data into the accumulator
and starts another conversion. A delay of 2.5
μ
s must be al-
lowed between conversions.
Figure 18. AD7824/AD7828–TMS32010 Interface
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| AD7834AR | 2.35V-5.25V, 12 bit, 1MSPS, Serial ADC 6-SOT-23 -40 to 125 |
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| AD7824BCHIPS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single-Ended Data Acquisition System |
| AD7824BQ | 功能描述:IC ADC 8BIT LC2MOS 4CH HS 24CDIP RoHS:否 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類(lèi)型:4 個(gè)單端，單極；2 個(gè)差分，單極 產(chǎn)品目錄頁(yè)面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| AD7824BQ/+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single-Ended Data Acquisition System |
| AD7824CQ | 功能描述:IC ADC 8BIT LC2MOS 4CH HS 24CDIP RoHS:否 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類(lèi)型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類(lèi)型:1 個(gè)單端，雙極 |
| AD7824CQ/+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single-Ended Data Acquisition System |
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