參數(shù)資料
型號(hào): AD7822
廠商: Analog Devices, Inc.
英文描述: 1-Channel Sampling ADCs(2MSPS,單通道采樣8位A/D轉(zhuǎn)換器)
中文描述: 單通道采樣ADC(2MSPS,單通道采樣8位的A / D轉(zhuǎn)換器)
文件頁數(shù): 12/20頁
文件大?。?/td> 238K
代理商: AD7822
AD7822/AD7825/AD7829
–12–
REV. 0
OPE RAT ING MODE S
T he AD7822, AD7825 and AD7829 have two possible modes
of operation, depending on the state of the
CONVST
pulse
approximately 100 ns after the end of a conversion, i.e., upon
the rising edge of the
EOC
pulse.
Mode 1 Operation (High Speed Sampling)
When the AD7822, AD7825 and AD7829 are operated in
Mode 1 they are not powered-down between conversions. T his
mode of operation allows high throughput rates to be achieved.
Figure 20 shows how this optimum throughput rate is achieved
by bringing
CONVST
high before the end of a conversion, i.e.,
before the
EOC
pulses low. When operating in this mode a new
conversion should not be initiated until 30 ns after the end of a
read operation. T his is to allow the track/hold to acquire the
analog signal to 0.5 LSB accuracy.
Figure 21. Mode 2 Operation
Mode 2 Operation (Automatic Power-Down)
When the AD7822, AD7825 and AD7829 are operated in
Mode 2 (see Figure 21), they automatically power down at the
end of a conversion. T he
CONVST
signal is brought low to
initiate a conversion and is left logic low until after the
EOC
goes high, i.e., approximately 100 ns after the end of the conver-
sion. T he state of the
CONVST
signal is sampled at this point
(i.e., 530 ns maximum after
CONVST
falling edge) and the
AD7822, AD7825 and AD7829 will power down as long as
CONVST
is low. T he ADC is powered up again on the rising
edge of the
CONVST
signal. Superior power performance can
be achieved in this mode of operation by only powering up the
AD7822, AD7825 and AD7829 to carry out a conversion. T he
parallel interface of the AD7822, AD7825 and AD7829 is still
fully operational while the ADCs are powered down. A read
may occur while the part is powered down, and so it does not
necessarily need to be placed within the
EOC
pulse as shown in
Figure 21.
Figure 20. Mode 1 Operation
t
2
t
1
t
3
VALID
DATA
CONVST
EOC
CS
RD
DB0-DB7
TRACK
HOLD
TRACK
HOLD
120ns
CONVST
EOC
CS
RD
DB0-DB7
t
POWER-UP
t
1
VALID
DATA
POWER
DOWN
HERE
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