參數(shù)資料
型號(hào): AD7276
廠商: Analog Devices, Inc.
元件分類: 串行ADC
英文描述: 3MSPS,12-/10-/8-Bit ADCs in 6-Lead TSOT
中文描述: 3MSPS,12/10/8位ADC的6引腳TSOT
文件頁(yè)數(shù): 8/20頁(yè)
文件大?。?/td> 255K
代理商: AD7276
8
REV. PrF
PRELIMINARY TECHNICAL DATA
AD7276/AD7277/AD7278
Preliminary Technical Data
PIN FUNCTION DESCRIPTION
Pin
Mnemonic
Function
Chip Select. Active low logic input. This input provides the dual function of initiating
conversion on the AD7276/AD7277/AD7278 and also frames the serial data transfer.
Power Supply Input. The V
DD
range for the AD7276/AD7277/AD7278 is from +2.35V to
+3.6V.
Analog Ground. Ground reference point for all circuitry on the AD7276/AD7277/AD7278.
All analog input signals should be referred to this GND voltage.
Analog Input. Single-ended analog input channel. The input range is 0 to V
DD
.
Data Out. Logic Output. The conversion result from the AD7276/AD7277/AD7278 is pro-
vided on this output as a serial data stream. The bits are clocked out on the falling edge of
the SCLK input. The data stream from the AD7276 consists of two leading zeros followed
by the 12 bits of conversion data followed by two trailing zeros, which is provided MSB
first. The data stream from the AD7277 consists of two leading zeros followed by the 10 bits
of conversion data followed by four trailing zeros, which is provided MSB first. The data
stream from the AD7278 consists of two leading zeros followed by the 8 bits of conversion
data followed by six trailing zeros, which is provided MSB first.
Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part.
This clock input is also used as the clock source for the AD7276/AD7277/AD7278's conver-
sion process.
V
DD
GND
V
IN
SDATA
SCLK
相關(guān)PDF資料
PDF描述
AD7276BRM 3MSPS,12-/10-/8-Bit ADCs in 6-Lead TSOT
AD7276BUJ-REEL 3MSPS,12-/10-/8-Bit ADCs in 6-Lead TSOT
AD7277 3MSPS,12-/10-/8-Bit ADCs in 6-Lead TSOT
AD7277BRM 3MSPS,12-/10-/8-Bit ADCs in 6-Lead TSOT
AD7277BUJ-REEL 3MSPS,12-/10-/8-Bit ADCs in 6-Lead TSOT
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