- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375147 > A63L7332SERIES (AMIC Technology Corporation) 128K X 32 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output PDF資料下載
參數(shù)資料
| 型號(hào)： | A63L7332SERIES |
| 廠商： | AMIC Technology Corporation |
| 元件分類： | 通用總線功能 |
| 英文描述： | 128K X 32 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output |
| 中文描述： | 128K的× 32位同步高的Burst計(jì)數(shù)器和流水線數(shù)據(jù)輸出高速SRAM |
| 文件頁(yè)數(shù)： | 7/17頁(yè) |
| 文件大?。?/td> | 381K |
| 代理商： | A63L7332SERIES |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)當(dāng)前第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)
A63L7332 Series
PRELIMINARY (December, 1998, Version 1.2)
6
AMIC Technology, Inc.
Notes: 1. X = "Disregard", H = Logic High, L = Logic Low.
2.
WRITE
= L means:
1) Any
BWx
(
BW1
,
BW2
,
BW3
, or
BW4
) and
BWE
are low or
2)
GW
is low.
3. All inputs except
OE
must be synchronized with setup and hold times around the rising edge (L-H) of CLK.
4. For write cycles that follow read cycles,
OE
must be HIGH before the input data request setup time and held
HIGH throughout the input data hold time.
5.
ADSP
LOW always initiates an internal Read at the L-H edge of CLK. A Write is performed by setting one or
more byte write enable signals and
BWE
LOW or
GW
LOW for the subsequent L-H edge of CLK. Refer to
the Write timing diagram for clarification.
Write Truth Table
Operation
GW
BWE
BW1
BW2
BW3
BW4
READ
H
H
X
X
X
X
READ
H
L
H
H
H
H
WRITE Byte 1
H
L
L
H
H
H
WRITE all bytes
H
L
L
L
L
L
WRITE all bytes
L
X
X
X
X
X
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A63L7332 | 128K X 32 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output |
| A63L7332E-42 | 128K X 32 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output |
| A63L7332E-45 | 128K X 32 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output |
| A63L7332E-5 | 128K X 32 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output |
| A63L73361E-6.5F | 128K X 36 Bit Synchronous High Speed SRAM with Burst Counter and Flow-through Data Output |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A63L7336 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:128K X 36 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output |
| A63L73361 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:128K X 36 Bit Synchronous High Speed SRAM with Burst Counter and Flow-through Data Output |
| A63L73361E | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:128K X 36 Bit Synchronous High Speed SRAM with Burst Counter and Flow-through Data Output |
| A63L73361E-6.5 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:128K X 36 Bit Synchronous High Speed SRAM with Burst Counter and Flow-through Data Output |
| A63L73361E-6.5F | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:128K X 36 Bit Synchronous High Speed SRAM with Burst Counter and Flow-through Data Output |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。