參數(shù)資料
型號(hào)： A63G7332
廠商： AMIC Technology Corporation
元件分類： 通用總線功能
英文描述： 128K X 32 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output
中文描述： 128K的× 32位同步高的Burst計(jì)數(shù)器和流水線數(shù)據(jù)輸出高速SRAM
文件頁(yè)數(shù)： 13/17頁(yè)
文件大小： 382K
代理商： A63G7332
A63G7332 Series
PRELIMINARY (December, 1998, Version 2.1)
12
AMIC Technology, Inc.
Timing Waveforms (continued)
CLK
ADSP
ADSC
ADDRESS
A1
A2
A3
OE
D(A2)
D(A2+1)
D(A2+2)
D(A2+3)
D(A3)
D(A3+1)
High-Z
DIN
t
AH
t
AS
t
ADSH
t
ADSS
t
ADSH
t
ADSS
t
KL
t
KH
t
KC
t
ADSH
t
ADSS
ADSC extends burst
GW
CE
(NOTE *2)
ADV
D(A1)
D(A2+1)
D(A3+2)
DOUT
BURST READ
Single WRITE
Extended BURST WRITE
t
OEHZ
t
DH
t
DS
(NOTE *3)
(NOTE *4)
ADV suspends burst
t
ADVH
t
ADVS
t
CEH
t
CES
t
WH
t
WS
BYTE WRITE signals are ignored
for first cycle when ADSP initiates burst
t
WH
t
WS
BWE,BW1-BW4
(NOTE *5)
(NOTE *1)
Write Timing
Notes: *1. D(A2) refers to output from address A2. D(A2+1) refers to output from the internal burst address immediately
following A2.
*2. Timing for
CE2
and CE2 is identical to that for
CE
. As shown in the above diagram, when
CE
is LOW,
CE2
is LOW and CE2 is HIGH. When
CE
is HIGH,
CE2
is HIGH and CE2 is LOW.
*3.
OE
must be HIGH before the input data setup, and held HIGH throughout the data hold period. This prevents
input/output data contention for the period prior to the time Byte Write enable inputs are sampled.
*4.
ADV
must be HIGH to permit a Write to the loaded address.
*5. Byte Write enables are decided by means of a Write truth table.
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