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參數(shù)資料
| 型號(hào)： | 90S1200 |
| 廠商： | Atmel Corp. |
| 元件分類： | 8位微控制器 |
| 英文描述： | -bit AVR Microcontroller with 8K Bytes In- System Programmable Flash |
| 中文描述： | 位AVR微控制器具有8K字節(jié)的系統(tǒng)內(nèi)可編程閃存 |
| 文件頁(yè)數(shù)： | 9/71頁(yè) |
| 文件大?。?/td> | 1416K |
| 代理商： | 90S1200 |
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9
AT90S1200
0838H
–
AVR
–
03/02
EEPROM Data Memory
The AT90S1200 contains 64 bytes of data EEPROM memory. It is organized as a sepa-
rate data space, in which single bytes can be read and written. The EEPROM has an
endurance of at least 100,000 write/erase cycles. The access between the EEPROM
and the CPU is described on page 25 specifying the EEPROM address register, the
EEPROM data register, and the EEPROM control register. For the SPI data download-
ing, see page 44 for a detailed description.
Instruction Execution
Timing
This section describes the general access timing concepts for instruction execution and
internal memory access.
The AVR CPU is driven by the System Clock
, directly generated from the external
clock crystal for the chip. No internal clock division is used.
Figure 11 shows the parallel instruction fetches and instruction executions enabled by
the Harvard architecture and the fast-access register file concept. This is the basic pipe-
lining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for
functions per cost, functions per clocks, and functions per power-unit.
Figure 11.
The Parallel Instruction Fetches and Instruction Executions
Figure 12 shows the internal timing concept for the register file. In a single clock cycle
an ALU operation using two register operands is executed, and the result is stored back
to the destination register.
Figure 12.
Single-cycle ALU Operation
System Clock
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
T1
T2
T3
T4
System Clock
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
T1
T2
T3
T4
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