參數(shù)資料
型號: 8XC51SLLOWVOLTAGE8XC51SL
廠商: Intel Corp.
英文描述: KEYBOARD CONTROLLER
中文描述: 鍵盤控制器
文件頁數(shù): 23/58頁
文件大?。?/td> 233K
代理商: 8XC51SLLOWVOLTAGE8XC51SL
2003 Oct 30
23
Philips Semiconductors
Product specification
Low power single card reader
TDA8029
Notes
1.
2.
Details on interaction with the UART behaviour in Power-down mode are described in Section 8.15.
Do not write logic 1s to reserved bits. These bits may be used in future 80C51 family products to invoke new features.
In that case, the reset or inactive value of the new bit will be logic 0, and its active value will be logic 1. The value
read from a reserved bit is indeterminate.
8.4.2
I
NTERRUPT
P
RIORITY
(IP)
REGISTER
Table 24
Interrupt priority register bits
Table 25
Description of register bits
Note
1.
Do not write logic 1s to reserved bits. These bits may be used in future 80C51 family products to invoke new features.
In that case, the reset or inactive value of the new bit will be logic 0, and its active value will be logic 1. The value
read from a reserved bit is indeterminate.
8.4.3
I
NTERRUPT
P
RIORITY
H
IGH
(IPH)
REGISTER
Table 26
Interrupt priority high register bits
Table 27
Description of register bits
2
EX1
External interrupt 1 enable.
EX1 = 1 enables the interrupt; EX1 = 0 disables the
interrupt.
Timer 0 interrupt enable.
ET0 = 1 enables the interrupt; ET0 = 0 disables the interrupt.
External interrupt 0 enable.
EX0 = 1 enables the interrupt; EX0 = 0 disables the
interrupt.
1
0
ET0
EX0
BIT
7
6
5
4
3
2
1
0
Symbol
PT2
PS
PT1
PX1
PT0
PX0
BIT
SYMBOL
DESCRIPTION
7 and 6
5
4
3
2
1
0
PT2
PS
PT1
PX1
PT0
PX0
Not implemented.
Reserved for future use; note 1.
Timer 2 interrupt priority.
See Table 20.
Serial port interrupt priority.
See Table 20.
Timer 1 interrupt priority.
See Table 20.
External interrupt 1 priority.
See Table 20.
Timer 0 interrupt priority.
See Table 20.
External interrupt 0 priority.
See Table 20.
BIT
7
6
5
4
3
2
1
0
Symbol
PT2H
PSH
PT1H
PX1H
PT0H
PX0H
BIT
SYMBOL
DESCRIPTION
7 and 6
5
4
3
PT2H
PSH
PT1H
Not implemented.
Reserved for future use; note 1.
Timer 2 interrupt priority.
See Table 20.
Serial port interrupt priority.
See Table 20.
Timer 1 interrupt priority.
See Table 20.
BIT
SYMBOL
DESCRIPTION
(1)
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