參數(shù)資料
型號: 8XC51
廠商: Intel Corp.
英文描述: CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
中文描述: CHMOS單片8位微控制器
文件頁數(shù): 6/58頁
文件大?。?/td> 233K
代理商: 8XC51
2003 Oct 30
6
Philips Semiconductors
Product specification
Low power single card reader
TDA8029
7
PINNING
SYMBOL
PIN
DESCRIPTION
P17
P16
1
2
general purpose I/O
general purpose I/O; card clock generation up to 20 MHz with three times synchronous
frequency doubling (f
XTAL
,
1
/
2
f
XTAL
,
1
/
4
f
XTAL
and
1
/
8
f
XTAL
)
supply voltage
ground connection
shut-down signal input; active LOW
connection for an external capacitor determining the Power-on reset pulse width
(typically 1 ms per 2 nF)
data input/output to/from the card (C7); 14 k
integrated pull-up resistor to V
CC
card presence detection contact (active HIGH); do not connect to any external pull-up
or pull-down resistor; use with a normally open presence switch
card ground (C5); connect to GND in the application
clock to the card (C3)
card supply voltage (C1)
card reset (C2)
output of the DC/DC converter (low ESR 220 nF to PGND)
DC/DC converter capacitor connection (low ESR 220 nF between SAP and SAM)
DC/DC converter capacitor connection (low ESR 220 nF between SBP and SBM)
power input for the DC/DC converter
DC/DC converter capacitor connection (low ESR 220 nF between SBP and SBM)
ground for the DC/DC converter
DC/DC converter capacitor connection (low ESR 220 nF between SAP and SAM)
used for test purpose; connect to GND in the application
control signal for microcontroller; connect to V
DD
in the application
control signal for the microcontroller; leave open in the application
control signal for the microcontroller; leave open in the application
general purpose I/O
general purpose I/O
external crystal connection or input for an external clock signal
external crystal connection; leave open if an external clock is applied to XTAL1
reset input from the host (active HIGH); integrated pull-down resistor to GND
interrupt signal from the smart card interface; leave open in the application
external interrupt input or general purpose I/O; may be left open if not used
transmission line for serial communication with the host
reception line for serial communication with the host
V
DD
GND
SDWN_N
CDEL
3
4
5
6
I/O
PRES
7
8
GNDC
CLK
V
CC
RST
VUP
SAP
SBP
DCIN
SBM
PGND
SAM
TEST
EA_N
ALE
PSEN_N
P27
P26
XTAL1
XTAL2
RESET
P32/INT0_N
P33/INT1_N
P31/TX
P30/RX
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
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