參數(shù)資料
    型號: 8XC51
    廠商: Intel Corp.
    英文描述: CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
    中文描述: CHMOS單片8位微控制器
    文件頁數(shù): 40/58頁
    文件大小: 233K
    代理商: 8XC51
    2003 Oct 30
    40
    Philips Semiconductors
    Product specification
    Low power single card reader
    TDA8029
    Table 64
    Description of register bits
    Table 65
    Clock value for an asynchronous card
    BIT
    SYMBOL
    DESCRIPTION
    7 and 6
    5
    SHL
    Not used.
    Select HIGH Level.
    This bit determines how the clock is stopped when bit CST = 1. If
    SHL = 0, then the clock is stopped at LOW level, if SHL = 1 at HIGH level.
    Clock Stop.
    In case of an asynchronous card, bit CST defines whether the clock to the
    card is stopped or not. If CST = 1, then the clock is stopped. If CST = 0, then the clock is
    determined by bits AC[2:0] according to Table 65. All frequency changes are
    synchronous, ensuring that no spike or unwanted pulse width occurs during changes
    Synchronous Clock.
    In the event of a synchronous card, then pin CLK is the copy of the
    value of bit SC. In reception mode, the data from the card is available to bit UR0 after a
    read operation of register URR. In transmission mode, the data is written on the I/O line
    of the card when register UTR has been written to.
    Asynchronous card clock.
    When CST = 0, the clock is determined by the state of these
    bits according to Table 65.
    4
    CST
    3
    SC
    2 to 0
    AC[2:0]
    f
    int
    is the frequency delivered by the internal oscillator clock circuitry.
    For switching from
    1
    /
    n
    f
    XTAL
    to
    1
    /
    2
    f
    int
    and reverse, only the bit AC2 must be changed (AC1
    and AC0 must remain the same). For switching from
    1
    /
    n
    f
    XTAL
    or
    1
    /
    2
    f
    int
    to stopped clock
    and reverse, only bits CST and SHL must be changed.
    When switching from
    1
    /
    n
    f
    XTAL
    to
    1
    /
    2
    f
    int
    and reverse, a delay can occur between the
    command and the effective frequency change on pin CLK. The fastest switch is from
    1
    /
    2
    f
    XTAL
    to
    1
    /
    2
    f
    int
    and reverse, the best regarding duty cycle is from
    1
    /
    8
    f
    XTAL
    to
    1
    /
    2
    f
    int
    and
    reverse. The bit CLKSW in register MSR tells the effective switch moment.
    In case of f
    CLK
    = f
    XTAL
    , the duty cycle must be ensured by the incoming clock signal on
    pin XTAL1.
    AC2
    AC1
    AC0
    CLOCK
    0
    0
    0
    0
    1
    0
    0
    1
    1
    0
    0
    1
    0
    1
    0
    f
    XTAL
    1
    /
    2
    f
    XTAL
    1
    /
    4
    f
    XTAL
    1
    /
    8
    f
    XTAL
    1
    /
    2
    f
    int
    1
    0
    1
    1
    /
    2
    f
    int
    1
    1
    0
    1
    /
    2
    f
    int
    1
    1
    1
    1
    /
    2
    f
    int
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