參數(shù)資料
型號(hào)： 8XC51
廠商： Intel Corp.
英文描述： CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
中文描述： CHMOS單片8位微控制器
文件頁(yè)數(shù)： 22/58頁(yè)
文件大?。?/td> 233K
代理商： 8XC51
2003 Oct 30
22
Philips Semiconductors
Product specification
Low power single card reader
TDA8029
8.4
Interrupt priority structure
The TDA8029 has a 6-source 4-level interrupt structure.
There are three SFRs associated with the 4-level interrupt: IE, IP and IPH. The Interrupt Priority High (IPH) register
implements the 4-level interrupt structure. The IPH is located at SFR address B7h.
The function of the IPH is simple and when combined with the IP determines the priority of each interrupt. The priority of
each interrupt is determined as shown in Table 20.
Table 20
Priority bits
Table 21
Interrupt table
Notes
1.
2.
Level activated.
Transition activated.
8.4.1
I
NTERRUPT
E
NABLE
(IE)
REGISTER
Table 22
Interrupt enable register bits
Table 23
Description of register bits
IPH BIT n
IP BIT n
INTERRUPT PRIORITY LEVEL
0
0
1
1
0
1
0
1
level 0 (lowest priority)
level 1
level 2
level 3 (highest priority)
SOURCE
POLLING PRIORITY
REQUEST BITS
HARDWARE CLEAR
VECTOR ADDRESS
(HEX)
X0
T0
X1
T1
SP
T2
1
2
3
4
5
6
IE0
TF0
IE1
TF1
RI, TI
TF2, EXF2
N
(1)
; Y
(2)
Y
N
(1)
; Y
(2)
Y
N
N
03
0B
13
1B
23
2B
BIT
7
6
5
4
3
2
1
0
Symbol
EA
ET2
ES
ET1
EX1
ET0
EX0
BIT
SYMBOL
DESCRIPTION
(1)
7
EA
Global disable.
If EA = 0, all interrupts are disabled; If EA = 1, each interrupt can be
individually enabled or disabled by setting or clearing its enable bit.
Not implemented.
Reserved for future use; note 2.
Timer 2 interrupt enable.
ET2 = 1 enables the interrupt; ET2 = 0 disables the interrupt.
Serial port interrupt enable.
ES = 1 enables the interrupt; ES = 0 disables the interrupt.
Timer 1 interrupt enable.
ET1 = 1 enables the interrupt; ET1 = 0 disables the interrupt.
6
5
4
3
ET2
ES
ET1
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