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參數(shù)資料
| 型號： | 853054AL |
| 英文描述： | 4:1, DIFFERENTIAL-TO-3.3V OR 2.5V LVPECL/ECL CLOCK MULTIPLEXER |
| 中文描述： | 4:1，差分至3.3V或2.5V的LVPECL / ECL時(shí)鐘復(fù)用器 |
| 文件頁數(shù)： | 9/15頁 |
| 文件大?。?/td> | 207K |
| 代理商： | 853054AL |
Integrated
Circuit
Systems, Inc.
853054AG
www.icst.com/products/hiperclocks.html
REV. A JANUARY 5, 2006
9
ICS853054
4:1, D
IFFERENTIAL
-
TO
-3.3V
OR
2.5V
LVPECL/ECL C
LOCK
M
ULTIPLEXER
PRELIMINARY
V
CC
- 2V
50
Ω
50
Ω
RTT
Z
o
= 50
Ω
Z
o
= 50
Ω
FOUT
FIN
RTT =
Z
o
1
((V
OH
+ V
OL
) / (V
CC
– 2)) – 2
3.3V
125
Ω
125
Ω
84
Ω
84
Ω
Z
o
= 50
Ω
Z
o
= 50
Ω
FOUT
FIN
The clock layout topology shown below is a typical termi-
nation for LVPECL outputs. The two different layouts men-
tioned are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, termi-
nating resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
drive 50
Ω
transmission lines. Matched impedance techniques
should be used to maximize operating frequency and mini-
mize signal distortion.
Figures 3A and 3B
show two different
layouts which are recommended only as guidelines. Other
suitable clock layouts may exist and it would be recommended
that the board designers simulate to guarantee compatibility
across all printed circuit and clock component process varia-
tions.
F
IGURE
3B. LVPECL O
UTPUT
T
ERMINATION
F
IGURE
3A. LVPECL O
UTPUT
T
ERMINATION
T
ERMINATION
FOR
3.3V LVPECL O
UTPUTS
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