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參數(shù)資料
| 型號(hào)： | 853054AG |
| 英文描述： | 4:1, DIFFERENTIAL-TO-3.3V OR 2.5V LVPECL/ECL CLOCK MULTIPLEXER |
| 中文描述： | 4:1，差分至3.3V或2.5V的LVPECL / ECL時(shí)鐘復(fù)用器 |
| 文件頁數(shù)： | 5/15頁 |
| 文件大?。?/td> | 207K |
| 代理商： | 853054AG |
Integrated
Circuit
Systems, Inc.
853054AG
www.icst.com/products/hiperclocks.html
REV. A JANUARY 5, 2006
5
ICS853054
4:1, D
IFFERENTIAL
-
TO
-3.3V
OR
2.5V
LVPECL/ECL C
LOCK
M
ULTIPLEXER
PRELIMINARY
A
DDITIVE
P
HASE
J
ITTER
Additive Phase Jitter, RMS
@ 155.52MHz = <0.238ps typical
0
-10
-20
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-60
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1k
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1M
10M
100M
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise.
This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental. This
ratio is expressed in decibels (dBm) or a ratio of the power in
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The de-
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a
dBc
value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
vice meets the noise floor of what is shown, but can actually be
lower. The phase noise is dependant on the input source and
measurement equipment.
O
FFSET
F
ROM
C
ARRIER
F
REQUENCY
(H
Z
)
S
H
O
Z
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 853054AL | 4:1, DIFFERENTIAL-TO-3.3V OR 2.5V LVPECL/ECL CLOCK MULTIPLEXER |
| 854660 | Analog Filter |
| 854661 | Analog Filter |
| 854662 | Analog Filter |
| 854663 | Analog Filter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 853054AGLF | 制造商:IDT from Components Direct 功能描述:IDT 853054AGLF CLOCK MANAGEMENT - Rail/Tube 制造商:IDT 功能描述:IDT 853054AGLF Clock Management 制造商:Integrated Device Technology Inc 功能描述:IC CLK MULTPX 4:1 3.2GHZ 16TSSOP |
| 853054AL | 制造商:ICS 制造商全稱:ICS 功能描述:4:1, DIFFERENTIAL-TO-3.3V OR 2.5V LVPECL/ECL CLOCK MULTIPLEXER |
| 853058AG | 制造商:Integrated Device Technology Inc 功能描述:Clock Multiplexer 8-IN ECL/LVPECL 24-Pin TSSOP Tube 制造商:IDT from Components Direct 功能描述:IDT 853058AG CLOCK MANAGEMENT - Rail/Tube 制造商:IDT 功能描述:IDT 853058AG Clock Management |
| 853058AGLF | 制造商:Integrated Device Technology Inc 功能描述:IC CLK MULTPX 8:1 2.8GHZ 24TSSOP |
| 8530-5913-9500 | 制造商:CRU 功能描述:DATAPORT 25 SECURE, COMPLETE ASSEMBLY, SATA, 256-BIT AES ENC - Bulk |
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