參數(shù)資料
型號: MDS212CG
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 網(wǎng)絡接口
英文描述: 12-Port 10/100Mbps Ethernet Switch
中文描述: DATACOM, LAN SWITCHING CIRCUIT, PBGA456
封裝: 35 X 35 MM, 2.33 MM HEIGHT, MS-034, HSBGA-456
文件頁數(shù): 64/111頁
文件大?。?/td> 1609K
代理商: MDS212CG
MDS212
Data Sheet
64
Zarlink Semiconductor Inc.
FCR
Flooding Control Register
6DC
W/R
MCAT
MCT Aging Timer
6E0
W/R
TPMXR
Trunk Port Mapping Table Index Register
6E4
W/--
TPMTD
Trunk Port Mapping Table Data Register
6E8
W/R
PTR
Pacing Time Regulation
6EC
W/R
MTCR
MCT Threshold & Counter Register
6F0
W/R
7. Link List Management
LKS
Link List Status Register
680
W/R
AMBX
Mail Box Access Port
684
W/R
AFML
Free Mail Box List Access Port
688
W/R
8. Access Control Function Group 1 (Chip Level controls)
AVTC
VLAN Type Code
648
W/R
AXSC
Transmission Scheduling Control Register
64C
W/R
ATTL
Transmission Timing & Threshold Control Register
650
W/R
AMIIC
MII Command Register
654
W/--
AMIIS
MII Status Register
658
--/R
AFCRIA
Flow Control Ram Input Address
65C
W/--
AFCRID0
Flow Control Ram Input Data
660
W/R
AFCRID1
Flow Control Ram Input Data
664
W/R
AFCR
Flow Control Register
670
W/R
AMAR0
Multicast Addr. For MAC Control Frames Byte [3,2,1,0]
674
W/R
AMAR1
Multicast Addr. For MAC Control Frames Byte [5,4]
678
W/R
AMCT
MAC Control Frame Type Code Register
67C
W/R
ADAR0
Base MAC Address Register - Byte [3,2,1,0]
600
W/R
ADAR1
Base MAC Address Register - Byte [5,4]
604
W/R
ADAOR0
MAC Offset Address Register Port [0:7]
608
W/R
ADAOR1
MAC Offset Address Register Port [12:8]
60C
W/R
ACKTM
Timer For SOF Check
610
W/R
AFCOFT10
Flow Control Off Time for 10Mbps port
614
W/R
AFCOFT100
Flow Control Off Time for 100Mbps port
618
W/R
AFCHT10
Flow Control Holding Time for 10Mbps port
620
W/R
AFCHT100
Flow Control Holding Time for 100Mbps port
624
W/R
9. Access Control Function Group 2 (Chip Level controls)
APMR
Port Mirroring Register
5C0
W/R
Tag
Description
Address
W/R
Table 9 - MDS212 Register Map (continued)
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