參數(shù)資料
型號: 74VHCT03AMTR
廠商: 意法半導(dǎo)體
英文描述: QUAD 2-INPUT OPEN DRAIN NAND GATE
中文描述: 四2輸入與非門開漏
文件頁數(shù): 1/8頁
文件大?。?/td> 158K
代理商: 74VHCT03AMTR
1/8
June 2001
I
HIGH SPEED: t
PZ
= 3.9 ns (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION:
I
CC
= 2
μ
A (MAX.) at T
A
=25°C
COMPATIBLE WITH TTL OUTPUTS:
V
IH
= 2V (MIN.), V
IL
= 0.8V (MAX)
POWER DOWN PROTECTION ON INPUTS
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 4.5V to 5.5V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 03
IMPROVED LATCH-UP IMMUNITY
LOW NOISE: V
OLP
= 0.8V (MAX.)
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I
I
I
I
I
I
DESCRIPTION
The 74VHCT03A is an advanced high-speed
CMOS QUAD 2-INPUT OPEN DRAIN NAND
GATE fabricated with sub-micron silicon gate and
double-layer metal wiring C
2
MOS technology.
The internal circuit is composed of 3 stages
including buffer output, which provides high noise
immunity and stable output.
This device can, with an external pull-up resistor,
be used in wired AND configuration. This device
can also be used as a led driver and in any other
application requiring a current sink.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V since all inputs are
equipped with TTL threshold.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74VHCT03A
QUAD 2-INPUT OPEN DRAIN NAND GATE
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
PACKAGE
TUBE
T & R
SOP
TSSOP
74VHCT03AM
74VHCT03AMTR
74VHCT03ATTR
TSSOP
SOP
相關(guān)PDF資料
PDF描述
74VHCT03ATTR QUAD 2-INPUT OPEN DRAIN NAND GATE
74VHCT03AM QUAD 2-INPUT OPEN DRAIN NAND GATE
74VHCT03AT QUAD 2-INPUT OPEN DRAIN NAND GATE
74VHCT04AM Octal Buffers And Line Drivers With 3-State Outputs 20-TSSOP -40 to 85
74VHCT04AT CERAMIC CHIP/MIL-PRF-55681
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