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參數(shù)資料
| 型號： | 74AC169SJ |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Synchronous Up/Down Counter |
| 中文描述： | AC SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, PDSO16 |
| 封裝： | 5.30 MM, EIAJ TYPE2, SOP-16 |
| 文件頁數(shù)： | 2/8頁 |
| 文件大?。?/td> | 103K |
| 代理商： | 74AC169SJ |
www.fairchildsemi.com
2
7
Functional Description
The AC169 uses edge-triggered J-K-type flip-flops and
have no constraints on changing the control or data input
signals in either state of the Clock. The only requirement is
that the various inputs attain the desired state at least a
setup time before the rising edge of the clock and remain
valid for the recommended hold time thereafter. The paral-
lel load operation takes precedence over the other opera-
tions, as indicated in the Mode Select Table. When PE is
LOW, the data on the P
0
–
P
3
inputs enters the flip-flops on
the next rising edge of the Clock. In order for counting to
occur, both CEP and CET must be LOW and PE must be
HIGH; the U/D input then determines the direction of count-
ing. The Terminal Count (TC) output is normally HIGH and
goes LOW, provided that CET is LOW, when a counter
reaches zero in the Count Down mode or reaches 15 in the
Count Up mode. The TC output state is not a function of
the Count Enable Parallel (CEP) input level. If an illegal
state occurs, the AC169 will return to the legitimate
sequence within two counts. Since the TC signal is derived
by decoding the flip-flop states, there exists the possibility
of decoding spikes on TC. For this reason the use of TC as
a clock signal is not recommended (see logic equations
below).
1. Count Enable
=
CEP
CET
PE
2. Up: TC
=
Q
0
Q
1
Q
2
Q
3
(Up)
CET
3. Down: TC
=
Q
0
Q
1
Q
2
Q
3
(Down)
CET
Mode Select Table
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
State Diagram
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
PE
CEP
CET
U/D
Action on Rising
Clock Edge
L
X
X
X
Load (P
n
to Q
n
)
Count Up (Increment)
H
L
L
H
H
L
L
L
Count Down (Decrement)
H
H
X
X
No Change (Hold)
H
X
H
X
No Change (Hold)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74AC169SJ_Q | 功能描述:計(jì)數(shù)器 IC 4-Stage Syn Bidi Ctr RoHS:否 制造商:NXP Semiconductors 計(jì)數(shù)器類型:Binary Counters 邏輯系列:74LV 位數(shù):10 計(jì)數(shù)法: 計(jì)數(shù)順序: 工作電源電壓:1 V to 5.5 V 工作溫度范圍:- 40 C to + 125 C 封裝 / 箱體:SOT-109 封裝:Reel |
| 74AC169SJX | 功能描述:計(jì)數(shù)器移位寄存器 4-Stage Syn Bidi Ctr RoHS:否 制造商:Texas Instruments 計(jì)數(shù)器類型: 計(jì)數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
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| 74AC174 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Hex D-Type Flip-Flop with Master Reset |
| 74AC174_01 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:HEX D-TYPE FLIP FLOP WITH CLEAR |
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