參數(shù)資料
型號(hào)： 72825LB15PFI9
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： FIFO
英文描述： 1K X 18 BI-DIRECTIONAL FIFO, 10 ns, PQFP128
封裝： TQFP-128
文件頁(yè)數(shù)： 26/26頁(yè)
文件大?。?/td> 336K
代理商： 72825LB15PFI9
9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72805LB/72815LB/72825LB/72835LB/72845LB CMOS Dual SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
NOTES:
1. In a daisy-chain depth expansion,
FL is held LOW for the "first load device". The RXI and WXI inputs are driven by the corresponding RXO and WXO outputs of the preceding device.
2. In a daisy-chain depth expansion,
FL is held HIGH for members of the expansion other than the "first load device". The RXI and WXI inputs are driven by the corresponding RXO and
WXO outputs of the preceding device.
TABLE 3 — TRUTH TABLE FOR CONFIGURATION AT RESET
FL
RXI
WXI
EF/OR
FF/IR
PAE, PAF
FIFO TIMING MODE
0
Single register-buffered
Asynchronous
Standard
Empty Flag
Full Flag
0
1
Triple register-buffered
Double register-buffered
Asynchronous
FWFT
Output Ready Flag
Input Ready Flag
0
1
0
Double register-buffered
Asynchronous
Standard
Empty Flag
Full Flag
0(1)
1
Single register-buffered
Asynchronous
Standard
Empty Flag
Full Flag
1
0
Single register-buffered
Synchronous
Standard
Empty Flag
Full Flag
1
0
1
Triple register-buffered
Double register-buffered
Synchronous
FWFT
Output Ready Flag
Input Ready Flag
1
0
Double register-buffered
Synchronous
Standard
Empty Flag
Full Flag
1(2)
1
Single register-buffered
Asynchronous
Standard
Empty Flag
Full Flag
TABLE 4 — REGISTER-BUFFERED FLAG OUTPUT OPTIONS — IDT STANDARD MODE
Empty Flag (
EF)
Full Flag (
FF)
Partial Flags
Programming at Reset
Flag Timing
Buffered Output
Timing Mode
FL
RXI
WXI
Diagrams
Single
Asynch
0
Figure 9, 10
Single
Sync
1
0
Figure 9, 10
Double
Asynch
0
1
0
Figure 24, 26
Double
Synch
1
0
Figure 24, 26
TABLE 5 — REGISTER-BUFFERED FLAG OUTPUT OPTIONS — FWFT MODE
Output Ready (
OR)
Input Ready (
IR)
Partial Flags
Programming at Reset
Flag Timing
FL
RXI
WXI
Diagrams
Triple
Double
Asynch
0
1
Figure 27
Triple
Double
Sync
1
0
1
Figure 20, 21
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