參數(shù)資料
型號(hào)： 72825LB15PFI9
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： FIFO
英文描述： 1K X 18 BI-DIRECTIONAL FIFO, 10 ns, PQFP128
封裝： TQFP-128
文件頁(yè)數(shù)： 21/26頁(yè)
文件大?。?/td> 336K
代理商： 72825LB15PFI9
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72805LB/72815LB/72825LB/72835LB/72845LB CMOS Dual SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
4
Symbol
Name
I/O
Description
DA0–DA17
DataInputs
I
Data inputs for an 18-bit bus.
DB0-DB17
RSA
Reset
I
When
RS is set LOW, internal read and write pointers are set to the first location of the RAM array, FF and
RSB
PAF go HIGH, and PAE and EF go LOW. A reset is required before an initial WRITE after power-up.
WCLKA
Write Clock
I
When
WEN is LOW, data is written into the FIFO on a LOW-to-HIGH transition of WCLK, if the FIFO is not full.
WCLKB
WENA
Write Enable
I
When
WEN is LOW, data is written into the FIFO on every LOW-to-HIGH transition of WCLK. When WEN is
WENB
HIGH, the FIFO holds the previous data. Data will not be written into the FIFO if the
FF is LOW.
RCLKA
Read Clock
I
When
REN is LOW, data is read from the FIFO on a LOW-to-HIGH transition of RCLK, if the FIFO is not empty.
RCLKB
RENA
Read Enable
I
When
REN is LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK. When REN is HIGH,
RENB
the output register holds the previous data. Data will not be read from the FIFO if the
EF is LOW.
OEA
Output Enable
I
When
OE is LOW, the data output bus is active. If OE is HIGH, the output data bus will be in a high-impedance
OEB
state.
LDA
Load
I
When
LD is LOW, data on the inputs D0–D11 is written to the offset and depth registers on the LOW-to-HIGH
LDB
transition of the WCLK, when
WEN is LOW. When LD is LOW, data on the outputs Q0–Q11 is read from the
offset and depth registers on the LOW-to-HIGH transition of the RCLK, when
REN is LOW.
FLA
First Load
I
In the single device or width expansion configuration,
FL together with WXI and RXI determine if the mode is
FLB
IDT Standard mode or First Word Fall Through (FWFT) mode, as well as whether the
PAE/PAF flags are
synchronous or asynchronous. (See Table I.) In the Daisy Chain Depth Expansion configuration,
FL is grounded
on the first device (first load device) and set to HIGH for all other devices in the Daisy Chain.
WXIA
Write Expansion
I
In the single device or width expansion configuration,
WXI together with FL and RXI determine if the mode is
WXIB
Input
IDT Standard mode or FWFT mode, as well as whether the
PAE/PAF flags are synchronous or asynchronous.
(See Table 1.) In the Daisy Chain Depth Expansion configuration,
WXI is connected to WXO (Write Expansion
Out) of the previous device.
RXIA
Read Expansion
I
In the single device or width expansion configuration,
RXI together with FL and WXI, determine if the mode is
RXIB
Input
IDT Standard mode or FWFT mode, as well as whether the
PAE/PAF flags are synchronous or asynchronous.
(See Table 1.) In the Daisy Chain Depth Expansion configuration,
RXI is connected to RXO (Read Expansion
Out) of the previous device.
FFA/IRA
Full Flag/
O
In the IDT Standard mode, the
FF function is selected FF indicates whether or not the FIFO memory is full. In
FFB/IRB
Input Ready
the FWFT mode, the
IR function is selected. IR indicates whether or not there is space available for writing to
the FIFO memory.
EFA/ORA
Empty Flag/
O
In the IDT Standard mode, the
EF function is selected. EF indicates whether or not the FIFO memory is empty.
EFB/ORB
Output Ready
In FWFT mode, the
OR function is selected. OR indicates whether or not there is valid data available at the
outputs.
PAEA
Programmable
O
When
PAE is LOW, the FIFO is almost-empty based on the offset programmed into the FIFO. The default
PAEB
Almost-Empty flag
offset at reset is 31 from empty for IDT72805LB, 63 from empty for IDT72815LB, and 127 from empty for
IDT72825LB/72835LB/72845LB.
PAFA
Programmable
O
When
PAF is LOW, the FIFO is almost-full based on the offset programmed into the FIFO. The default offset
PAFB
Almost-Full flag
at reset is 31 from full for IDT72805LB, 63 from full for IDT72815LB, and 127 from full for IDT72825LB/72835LB/
72845LB.
WXOA/HFA
Write Expansion
O
In the single device or width expansion configuration, the device is more than half full when
HF is LOW. In the
WXOB/HFB
Out/Half-Full Flag
depth expansion configuration, a pulse is sent from
WXO to WXI of the next device when the last location in
the FIFO is written.
RXOA
Read Expansion
O
In the depth expansion configuration, a pulse is sent from
RXO to RXI of the next device when the last location
RXOB
Out
in the FIFO is read.
QA0–QA17
Data Outputs
O
Data outputs for an 18-bit bus.
QB0-QB17
VCC
Power
+5V power supply pins.
GND
Ground
Ground pins.
PIN DESCRIPTION
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