參數(shù)資料
型號(hào)： 72825LB15PFI9
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi)： FIFO
英文描述： 1K X 18 BI-DIRECTIONAL FIFO, 10 ns, PQFP128
封裝： TQFP-128
文件頁(yè)數(shù)： 17/26頁(yè)
文件大?。?/td> 336K
代理商： 72825LB15PFI9
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72805LB/72815LB/72825LB/72835LB/72845LB CMOS Dual SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
24
Figure 30. Block Diagram of 8,192 x 18 Synchronous
FIFO Memory With Programmable Flags used in Depth Expansion Configuration
DEPTH EXPANSION CONFIGURATION — DAISY CHAIN TECHNIQUE
(WITH PROGRAMMABLE FLAGS)
These devices can easily be adapted to applications requiring more than
256/512/1,024/2,048/4,096 words of buffering. Figure 30 shows Depth
Expansion using one IDT72805LB/72815LB/72825LB/72835LB/72845LBs.
Maximum depth is limited only by signal loading. Follow these steps:
1.ThefirstdevicemustbedesignatedbygroundingtheFirstLoad(
FL)controlinput.
2. All other devices must have
FL in the HIGH state.
3. The Write Expansion Out (
WXO) pin of each device must be tied to the
Write Expansion In (
WXI) pin of the next device. See Figure 30.
4. The Read Expansion Out (
RXO) pin of each device must be tied to the
Read Expansion In (
RXI) pin of the next device. See Figure 30.
5. All Load (
LD) pins are tied together.
6. The Half-Full flag (
HF) is not available in this Depth Expansion
Configuration.
7.
EF, FF, PAE, and PAF are created with composite flags by ORing
together every respective flags for monitoring. The composite
PAE and
PAF flags are not precise.
8. In Daisy Chain mode, the flag outputs are single register-buffered and
the partial flags are in asynchronous timing mode.
LOAD
WRITE CLOCK
WRITE ENABLE
READ CLOCK
READ ENABLE
OUTPUT ENABLE
DATA IN
DATA OUT
RESET
FIRST LOAD (
FL)
Vcc
WXOA
WXIA
RXOA
RXIA
WXOB
WXIB
RXOB
RXIB
IDT72845
FFA/IRA
PAFA
EFA/ORA
PAEA
PAFB
PAEB
EF/OR
PAE
FF/IR
PAF
3139 drw 30
RCLKB
RENB
OEB
WCLKB
WENB
RSB
FLA
RCLKA
RENA
OEA
WCLKA
WENA
RSA
LDA
DAn
QAn
DBn
QBn
LDB
FIFO A
4,096 x 18
FIFO B
4,096 x 18
FFA/IRA EFA/ORA
相關(guān)PDF資料
PDF描述
7283-1019 1 CONTACT(S), FEMALE, COMBINATION LINE CONNECTOR
7283-1114 1 CONTACT(S), FEMALE, COMBINATION LINE CONNECTOR
7283-4421 2 CONTACT(S), FEMALE, COMBINATION LINE CONNECTOR
7283-1064 6 CONTACT(S), FEMALE, COMBINATION LINE CONNECTOR
7283-1118 11 CONTACT(S), FEMALE, COMBINATION LINE CONNECTOR
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
72825LB25BG 功能描述:先進(jìn)先出 RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線(xiàn)寬度:18 bit 總線(xiàn)定向:Unidirectional 存儲(chǔ)容量:4 Mbit 定時(shí)類(lèi)型:Synchronous 組織:256 K x 18 最大時(shí)鐘頻率:100 MHz 訪問(wèn)時(shí)間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝:
72825LB25BG8 制造商:Integrated Device Technology Inc 功能描述:FIFO Mem Sync Quad Depth/Width Bi-Dir 1K x 18 x 2 121-Pin BGA T/R 制造商:Integrated Device Technology Inc 功能描述:FIFO SYNC QUAD DEPTH/WIDTH BI-DIR 1KX18X2 121BGA - Tape and Reel
72825LB25PF 功能描述:先進(jìn)先出 RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線(xiàn)寬度:18 bit 總線(xiàn)定向:Unidirectional 存儲(chǔ)容量:4 Mbit 定時(shí)類(lèi)型:Synchronous 組織:256 K x 18 最大時(shí)鐘頻率:100 MHz 訪問(wèn)時(shí)間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝:
72825LB25PF8 功能描述:先進(jìn)先出 RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線(xiàn)寬度:18 bit 總線(xiàn)定向:Unidirectional 存儲(chǔ)容量:4 Mbit 定時(shí)類(lèi)型:Synchronous 組織:256 K x 18 最大時(shí)鐘頻率:100 MHz 訪問(wèn)時(shí)間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝:
7282-5PG-300 功能描述:標(biāo)準(zhǔn)環(huán)形連接器 5P PIN PANEL MNT RoHS:否 制造商:Hirose Connector 系列:EM-W 產(chǎn)品類(lèi)型:Accessories 位置/觸點(diǎn)數(shù)量:1 觸點(diǎn)類(lèi)型: 觸點(diǎn)電鍍: 安裝風(fēng)格:Cable 外殼材質(zhì): 端接類(lèi)型:Clamp 電壓額定值:
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*