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參數(shù)資料
| 型號： | DS2433X |
| 廠商： | DALLAS SEMICONDUCTOR |
| 元件分類： | Programmable ROM |
| 英文描述： | 4K X 1 1-WIRE SERIAL EEPROM, UUC2 |
| 封裝： | DIE |
| 文件頁數(shù)： | 2/19頁 |
| 文件大小： | 457K |
| 代理商： | DS2433X |
DS2433
10 of 19
HARDWARE CONFIGURATION Figure 8
*5k
is adequate for reading the DS2433. To write to a single device, a 2.2k resistor and V
PUP of at
least 4.0V is sufficient. For writing multiple DS2433s simultaneously or operation at low VPUP, the
resistor should be bypassed by a low-impedance pullup to VPUP while the device copies the scratchpad to
EEPROM.
1-WIRE BUS SYSTEM
The 1-Wire bus is a system which has a single bus master and one or more slaves. In all instances the
DS2433 is a slave device. The bus master is typically a micro-controller. The discussion of this bus
system is broken down into three topics: hardware configuration, transaction sequence, and 1-Wire
signaling (signal types and timing). A 1-Wire protocol defines bus transactions in terms of the bus state
during specific time slots that are initiated on the falling edge of sync pulses from the bus master. For a
more detailed protocol description, refer to Chapter 4 of the Book of DS19xx iButton Standards.
HARDWARE CONFIGURATION
The 1-Wire bus has only a single line by definition; it is important that each device on the bus be able to
drive it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must have open
drain or 3-state outputs. The 1-Wire port of the DS2433 is open drain with an internal circuit equivalent
to that shown in Figure 8. A multidrop bus consists of a 1-Wire bus with multiple slaves attached. At
regular speed the 1-Wire bus has a maximum data rate of 16.3k bits per second. The speed can be
boosted to 142k bits per second by activating the Overdrive Mode. The 1-Wire bus requires a pullup
resistor of approximately 5k
.
The idle state for the 1-Wire bus is high. If for any reason a transaction needs to be suspended, the bus
MUST be left in the idle state if the transaction is to resume. If this does not occur and the bus is left low
for more than 16
s (Overdrive Speed) or more than 120 s (regular speed), one or more devices on the
bus may be reset.
TRANSACTION SEQUENCE
The protocol for accessing the DS2433 via the 1-Wire port is as follows:
§ Initialization
§ ROM Function Command
§ Memory Function Command
§ Transaction/Data
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS2433S | 512 X 8 1-WIRE SERIAL EEPROM, PDSO8 |
| DS2434S | SPECIALTY MEMORY CIRCUIT, PDSO16 |
| DS2434 | SPECIALTY MEMORY CIRCUIT, PBCY3 |
| DS2435 | SPECIALTY MEMORY CIRCUIT, PBCY3 |
| DS2436B | SPECIALTY MEMORY CIRCUIT, PBCY3 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 532HB622M080BG | 制造商:SILABS 制造商全稱:SILABS 功能描述:DUAL FREQUENCY XO (10 MHZ TO 1.4 GHZ) |
| 532HB622M080BGR | 制造商:SILABS 制造商全稱:SILABS 功能描述:DUAL FREQUENCY XO (10 MHZ TO 1.4 GHZ) |
| 532HEX | 制造商:Belden Inc 功能描述: |
| 532JA622M080BG | 制造商:SILABS 制造商全稱:SILABS 功能描述:DUAL FREQUENCY XO (10 MHZ TO 1.4 GHZ) |
| 532JA622M080BGR | 制造商:SILABS 制造商全稱:SILABS 功能描述:DUAL FREQUENCY XO (10 MHZ TO 1.4 GHZ) |
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