參數(shù)資料
型號: 408364X
元件分類: 復位半導體
英文描述: 300mA LDO Linear Regulators with Internal Microprocessor Reset Circuit
中文描述: 集成電路釤高密度可編程邏輯器件
文件頁數(shù): 15/33頁
文件大?。?/td> 240K
代理商: 408364X
AMD
15
MACH230-18/24 (Ind)
CAPACITANCE (Note 1)
Parameter
Symbol
C
IN
C
OUT
Parameter Description
Input Capacitance
Test Conditions
V
IN
= 2.0 V V
CC
= 5.0 V, T
A
= 25
°
C
V
OUT
= 2.0 V f = 1 MHz
Typ
6
Unit
pF
Output Capacitance
8
pF
SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2)
Parameter
Symbol
t
PD
Parameter Description
Input, I/O, or Feedback to Combinatorial Output (Note 3)
Min
Max
18
Min
Max
24
Unit
ns
ns
D-type
12
16
T-type
13.5
17
ns
t
H
t
CO
t
WL
t
WH
Register Data Hold Time
Clock to Output (Note 3)
Clock
Width
0
0
ns
ns
ns
ns
12
14.5
LOW
HIGH
7.5
7.5
10
10
D-type
40
32
MHz
T-type
38
30.5
MHz
f
MAX
Maximum
Frequency
(Note 1)
D-type
53
38
MHz
T-type
44
34.5
MHz
66.5
50
MHz
t
SL
t
HL
t
GO
t
GWL
t
PDL
Setup Time from Input, I/O, or Feedback to Gate
Latch Data Hold Time
Gate to Output (Note 3)
Gate Width LOW
Input, I/O, or Feedback to Output Through Transparent
Input or Output Latch
Input Register Setup Time
Input Register Hold Time
Input Register Clock to Combinatorial Output
Input Register Clock to Output Register Setup
12
0
16
0
ns
ns
ns
ns
ns
13.5
14.5
7.5
10
20.5
26.5
t
SIR
t
HIR
t
ICO
t
ICS
2.5
3.5
2.5
4
ns
ns
ns
ns
22
28
D-type
18
24
T-type
19.5
25.5
ns
t
WICL
t
WICH
Input Register
Clock Width
LOW
HIGH
7.5
7.5
10
10
ns
ns
f
MAXIR
Maximum Input Register Frequency 1/(t
WICL
+ t
WICH
)
66.5
50
MHz
t
SIL
t
HIL
t
IGO
t
IGOL
Input Latch Setup Time
Input Latch Hold Time
Input Latch Gate to Combinatorial Output
Input Latch Gate to Output Through Transparent
Output Latch
Setup Time from Input, I/O, or Feedback Through
Transparent Input Latch to Output Latch Gate
Input Latch Gate to Output Latch Setup
Input Latch Gate Width LOW
Input, I/O, or Feedback to Output Through Transparent
Input and Output Latches
2.5
3.5
2.5
4
ns
ns
ns
ns
24
26.5
30
32.5
t
SLL
14.5
18
ns
t
IGS
t
WIGL
t
PDLL
19.5
7.5
25.5
10
ns
ns
ns
23
29
-18
-24
t
S
Setup Time from Input, I/O, or Feedback to Clock
External Feedback
Internal Feedback (f
CNT
)
No Feedback 1/(t
WL
+ t
WH
)
1/(t
S
+ t
CO
)
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