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| 型號(hào)： | 23711 |
| 英文描述： | Understanding Page Mode Flash Memory Devices |
| 中文描述： | 理解頁(yè)面模式閃存設(shè)備 |
| 文件頁(yè)數(shù)： | 5/5頁(yè) |
| 文件大小： | 89K |
| 代理商： | 23711 |
Understanding Page Mode Flash Memory Devices
4
low as possible. Ideally, in code, all branch target loca-
tions would be aligned at the beginning of pages,
branch instructions would be located at the end of
pages, with all the locations in between used by se-
quentially executed instructions. Ideally, all data struc-
tures would be aligned on page boundaries.
However, few if any code compilers have been opti-
mized to the point to align all branch targets on pro-
grammer defined boundaries. Some optimizing
compilers support specific techniques like instruction
reordering and loop unrolling which will produce longer
sequences of sequential instructions which in turn re-
duce code branching, but at the cost of lower code den-
sity. Code linkers can also start code modules at
specific addresses or boundaries to force alignment.
Extensive optimization of branch target locations would
require either manual code optimization or some kind
of code post-processor algorithm that would reorder in-
structions or insert No-Ops and recalculate the relative
branch addresses in order to force branch target align-
ment.
Data structure alignment is easier to control since sev-
eral compilers do support that function. One example is
the Microsoft compiler that comes with Visual Studio
6.0. One of the compile options is
/Zp[n],
or “Struct
Member Alignment,” where
n
is in bytes and can be 1,
2, 4, 8, or 16. Depending on what
n
is set to, the com-
piler will align data structures to the given page bound-
ary. For example,
/Zp16
would put structures on 16-
byte, or 8-word boundaries. However, this may lead to
an increase in the memory space required as unused
space may have to be inserted between each data
record in order to align the start of each record.
SUMMARY
Page Mode memory devices have been developed to
increase system performance in spite of the market de-
mands for higher density and lower voltage, that would
otherwise tend to reduce memory performance. By
changing the internal architecture, the Page Mode
memory allows for faster read access times within each
page. Using a Page Mode memory device can improve
performance while holding or reducing cost and power
consumption. But, the system must use the Page Mode
feature properly in order to fully take advantage of the
available performance advantage.
Trademarks
Copyright 2000 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
Expressflash is a trademark of Advanced Micro Devices, Inc.
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