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| 型號(hào)： | 23711 |
| 英文描述： | Understanding Page Mode Flash Memory Devices |
| 中文描述： | 理解頁(yè)面模式閃存設(shè)備 |
| 文件頁(yè)數(shù)： | 4/5頁(yè) |
| 文件大?。?/td> | 89K |
| 代理商： | 23711 |
3
Understanding Page Mode Flash Memory Devices
Example: Comparing A Page Mode Device
To A Standard Device
By comparing a page mode device and a standard de-
vice, the true advantage in speed can clearly be seen.
Let’s say that System A uses a Page mode flash mem-
ory device, and System B uses a comparable standard
flash memory device. Both systems are using the same
processor, and both flash devices have the same ran-
dom access time. Table 3 shows how much time is re-
quired by both systems to read eight consecutive bytes
from memory.
Table 3.
Chart Comparing Read Times Between Page and Standard Devices
Both systems require a t
ACC
of 90 ns to do the first ran-
dom access read. However, System A can now do sub-
sequent reads in 30 ns, whereas System B still
requires 90 ns to complete each and every read com-
mand. By adding all the access times together, you can
see that System A, using a Page mode memory de-
vice, can read almost 2.5 times as fast as System B.
Is The Speed Improvement Always
Constant
Although the previous example shows that a Page
mode memory device can be dramatically faster than a
standard flash, the improvement is not always con-
stant. The more the system reads from the same page,
the faster the average access time. The less the sys-
tem reads from the same page, the slower the average
access time. In order to obtain optimum performance
from a Page mode device, the system’s program
should be structured such that as many consecutive
reads as possible are from within the same page. This
could involve aligning frequently accessed data struc-
tures or loop and jump labels to start on page bound-
aries.
What About Program and Erase
Operations
Program commands work on one word/byte, and Erase
commands work on one sector at a time, just as they
do in standard Flash memories.
What Are The Requirements On A System
Using A Page Mode Flash
The system must provide memory interface logic that is
aware of the page address boundaries and the differ-
ence in access time between an initial access and a
subsequent access within the same page so that the
access time (number of wait states) can be adjusted
dynamically.
Fortunately, many microprocessors already have such
interface logic already integrated into their memory in-
terface. Table 4 describes some of these processors.
Table 4.
Processor Families And Examples From
Each Family
Software Implications
In order to take full advantage of the performance en-
hancement of the Page Mode feature, initial accesses
need to be minimized and page mode accesses need
to be maximized, making the average access time as
System A:
Am29PL160C
System B:
Comparable Standard Device
Byte 0
90 ns (t
ACC
)
90 ns (t
ACC
)
Byte 1
30 ns (t
PACC
)
90 ns
Byte 2
30 ns
90 ns
Byte 3
30 ns
90 ns
Byte 4
30 ns
90 ns
Byte 5
30 ns
90 ns
Byte 6
30 ns
90 ns
Byte 7
30 ns
90 ns
Total time
300 ns
720 ns
Processor family
Examples
Motorola PowerPC
MPC850
Motorola Coldfire
MCF5307, MCF5206e, MCF5206
Sharp ARM
LH77790
Hitachi SuperH RISC
SH7709 (SH-3)
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