參數(shù)資料
型號: MAX11102AUB+
廠商: Maxim Integrated Products
文件頁數(shù): 13/30頁
文件大?。?/td> 0K
描述: IC ADC 12BIT SPI/SRL 10UMAX-EP
其它有關文件: Automotive Product Guide
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 50
位數(shù): 12
采樣率(每秒): 2M
數(shù)據(jù)接口: MICROWIRE?,QSPI?,串行,SPI?
轉換器數(shù)目: 1
功率耗散(最大): 707.3mW
電壓電源: 單電源
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)裸露焊盤
供應商設備封裝: 10-µMAX-EP
包裝: 管件
輸入數(shù)目和類型: 2 個單端,單極
20
Maxim Integrated
2Msps/3Msps, Low-Power,
Serial 12-/10-/8-Bit ADCs
MAX11102/03/05/06/10/11/15/16/17
Pin Description
Pin Configurations
1
3
4
10
8
7
SCLK
OVDD
CHSEL
*CONNECT EXPOSED PAD TO GROUND PLANE.
DEVICES DO NOT OPERATE WHEN EP IS NOT CONNECTED TO GROUND!
AGND
REF
MAX11102
MAX11103
MAX11106
MAX11111
29
DOUT
AIN2
AIN1
56
CS
VDD
TDFN
TOP VIEW
EP*
+
TOP VIEW
+
TOP VIEW
GND
SCLK
AIN
16
CS
5
DOUT
VDD
MAX11105
MAX11110
MAX11115
MAX11116
MAX11117
SOT23
2
34
+
MAX
29
DOUT
AIN2
110
SCLK
AIN1
OVDD
AGND
38
CHSEL
REF
7
CS
VDD
6
MAX11102
MAX11103
4
5
PIN
NAME
FUNCTION
TDFN
MAX
SOT23
1
AIN1
Analog Input Channel 1. Single-ended analog input with respect to AGND with range
of 0V to VREF.
2
AIN2
Analog Input Channel 2. Single-ended analog input with respect to AGND with range
of 0V to VREF.
3
AIN
Analog Input Channel. Single-ended analog input with respect to GND with range of
0V to VDD.
2
GND
Ground. Connect GND to the GND ground plane.
3
AGND
Analog Ground. Connect AGND directly the GND ground plane.
4
REF
External Reference Input. REF defines the signal range of the input signal AIN1/AIN2:
0V to VREF. The range of VREF is 1V to VDD. Bypass REF to AGND with 10FF || 0.1FF
capacitor.
5
1
VDD
Positive Supply Voltage. Bypass VDD with a 10FF || 0.1FF capacitor to GND. VDD
range is 2.2V to 3.6V. For the SOT23 package, VDD also defines the signal range of
the input signal AIN: 0V to VDD.
6
CS
Active-Low Chip-Select Input. The falling edge of CS samples the analog input signal,
starts a conversion, and frames the serial data transfer.
7
CHSEL
Channel Select. Set CHSEL high to select AIN2 for conversion. Set CHSEL low to
select AIN1 for conversion.
8
OVDD
Digital Interface Supply for SCLK, CS, DOUT, and CHSEL. The OVDD range is 1.5V
to VDD. Bypass OVDD with a 10FF || 0.1FF capacitor to GND.
9
5
DOUT
Three-State Serial Data Output. ADC conversion results are clocked out on the falling
edge of SCLK, MSB first. See Figure 1.
10
4
SCLK
Serial Clock Input. SCLK drives the conversion process. DOUT is updated on the fall-
ing edge of SCLK. See Figures 2 and 3.
EP
GND
Exposed Pad (TDFN and FMAX only). Connect EP directly to a solid ground plane.
Devices do not operate unless EP is connected to ground!
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